soc/intel/apollolake: add LPDDR4 sku selection support

Instead of having all the mainboards put similar logic
into their own code provide common mechanism for memory
SKU selection. A function, meminit_lpddr4_by_sku(), is
added that selects the proper configuration based on the
SKU id and configuration passed in. LPDDR4 speed as well
as DRAM device density configuration is associated for
each logical channel per SKU id.

BUG=chrome-os-partner:54949
BRANCH=None
TEST=Built and used on reef for memory config.

Change-Id: Ifc6a734040bb61a58bc3d4c128a6420a71245c6c
Signed-off-by: Aaron Durbin <adurbin@chromuim.org>
Reviewed-on: https://review.coreboot.org/15559
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Furquan Shaikh <furquan@google.com>

1 files changed, 32 insertions, 0 deletions

diff --git a/src/soc/intel/apollolake/meminit.c b/src/soc/intel/apollolake/meminit.c
index 8b661c9568..89547690b3 100644
--- a/src/soc/intel/apollolake/meminit.c
+++ b/src/soc/intel/apollolake/meminit.c
@@ -211,3 +211,35 @@ void meminit_lpddr4_enable_channel(struct FSP_M_CONFIG *cfg, int logical_chan,
 		break;
 	}
 }
+
+void meminit_lpddr4_by_sku(struct FSP_M_CONFIG *cfg,
+				const struct lpddr4_cfg *lpcfg, size_t sku_id)
+{
+	const struct lpddr4_sku *sku;
+
+	if (sku_id >= lpcfg->num_skus) {
+		printk(BIOS_ERR, "Too few LPDDR4 SKUs: 0x%zx/0x%zx\n",
+			sku_id, lpcfg->num_skus);
+		return;
+	}
+
+	printk(BIOS_INFO, "LPDDR4 SKU id = 0x%zx\n", sku_id);
+
+	sku = &lpcfg->skus[sku_id];
+
+	meminit_lpddr4(cfg, sku->speed);
+
+	if (sku->ch0_density) {
+		printk(BIOS_INFO, "LPDDR4 Ch0 density = %d\n",
+			sku->ch0_density);
+		meminit_lpddr4_enable_channel(cfg, LP4_LCH0, sku->ch0_density,
+						lpcfg->swizzle_config);
+	}
+
+	if (sku->ch1_density) {
+		printk(BIOS_INFO, "LPDDR4 Ch1 density = %d\n",
+			sku->ch1_density);
+		meminit_lpddr4_enable_channel(cfg, LP4_LCH1, sku->ch1_density,
+						lpcfg->swizzle_config);
+	}
+}