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authorAamir Bohra <aamir.bohra@intel.com>2017-04-07 21:10:27 +0530
committerMartin Roth <martinroth@google.com>2017-04-11 17:04:13 +0200
commitbf6dfaefc2fd2f22e55e3227d8b023bcd992cae5 (patch)
tree4bc0ac0b15a0a49ebc0abf89f18774ee63ab2eaa /src/soc/intel/apollolake/include
parentc1f260e49a6af71025c9fee2cea10ee4f48186b2 (diff)
intel/soc/apollolake: Use intel/common/uart driver
Change-Id: I6829eca34d983cfcc86074ef593cd92236b25ac5 Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/19204 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc/intel/apollolake/include')
-rw-r--r--src/soc/intel/apollolake/include/soc/uart.h9
1 files changed, 7 insertions, 2 deletions
diff --git a/src/soc/intel/apollolake/include/soc/uart.h b/src/soc/intel/apollolake/include/soc/uart.h
index c7ba4a657a..b2b1bb8623 100644
--- a/src/soc/intel/apollolake/include/soc/uart.h
+++ b/src/soc/intel/apollolake/include/soc/uart.h
@@ -18,9 +18,14 @@
#ifndef _SOC_APOLLOLAKE_UART_H_
#define _SOC_APOLLOLAKE_UART_H_
-void lpss_console_uart_init(void);
+/*
+* M and N divisor values for clock frequency configuration.
+* These values get us a 1.836 MHz clock (ideally we want 1.843 MHz)
+*/
+#define CLK_M_VAL 0x025a
+#define CLK_N_VAL 0x7fff
/* Initialize the console UART including the pads for the configured UART. */
-void soc_console_uart_init(void);
+void pch_uart_init(void);
#endif /* _SOC_APOLLOLAKE_UART_H_ */