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authorAlexandru Gagniuc <alexandrux.gagniuc@intel.com>2016-05-18 10:26:53 -0700
committerMartin Roth <martinroth@google.com>2016-05-26 23:46:59 +0200
commit944655dadaf595bf655f266eb35ca2f17c8410eb (patch)
treee46e82eb696aa89d0450de77376be8aa4cd5f6e4 /src/soc/intel/apollolake/include
parentbbac5ace53d57ad9acb0f979850c6a5e72c5f874 (diff)
soc/apollolake: Use simpler macros for the northbridge PCI device
The NB_DEV_ROOT macro, is almost unreadable, as it depends on other stringified macros, and acts differently depending on the coreboot stage. For ramstage, it also hides a function call. Rewrite the macro in terms of more basic and readable macros. Change-Id: I9b7071d67c8d58926e9b01fadaa239db1120448c Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc@intel.com> Reviewed-on: https://review.coreboot.org/14890 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc/intel/apollolake/include')
-rw-r--r--src/soc/intel/apollolake/include/soc/pci_devs.h12
1 files changed, 3 insertions, 9 deletions
diff --git a/src/soc/intel/apollolake/include/soc/pci_devs.h b/src/soc/intel/apollolake/include/soc/pci_devs.h
index ec550e8810..d11b9a7172 100644
--- a/src/soc/intel/apollolake/include/soc/pci_devs.h
+++ b/src/soc/intel/apollolake/include/soc/pci_devs.h
@@ -17,26 +17,17 @@
#include <rules.h>
-#define _NB_DEVFN(slot) PCI_DEVFN(NB_DEV_SLOT_ ## slot, 0)
#define _LPSS_PCI_DEVFN(slot, func) PCI_DEVFN(LPSS_DEV_SLOT_##slot, func)
-
#if !defined(__SIMPLE_DEVICE__)
#include <device/device.h>
#include <device/pci_def.h>
-#define _NB_DEV(slot) dev_find_slot(0, _NB_DEVFN(slot))
#define _LPSS_PCI_DEV(slot, func) dev_find_slot(0, _LPSS_PCI_DEVFN(slot, func))
#else
#include <arch/io.h>
-#define _NB_DEV(slot) PCI_DEV(0, NB_DEV_SLOT_ ## slot, 0)
#define _LPSS_PCI_DEV(slot, func) PCI_DEV(0, LPSS_DEV_SLOT_##slot, func)
#endif
-/* North bridge devices */
-#define NB_DEV_SLOT_ROOT 0x00
-#define NB_DEVFN_ROOT _NB_DEVFN(ROOT)
-#define NB_DEV_ROOT _NB_DEV(ROOT)
-
/* LPSS UART */
#define LPSS_DEV_SLOT_UART 0x18
#define LPSS_DEVFN_UART0 _LPSS_PCI_DEVFN(UART, 0)
@@ -48,6 +39,9 @@
#define LPSS_DEV_UART2 _LPSS_PCI_DEV(UART, 2)
#define LPSS_DEV_UART3 _LPSS_PCI_DEV(UART, 3)
+#define NB_BUS 0
+#define NB_DEVFN PCI_DEVFN(0, 0)
+#define NB_DEV_ROOT PCI_DEV(NB_BUS, 0x0, 0)
#define P2SB_DEV PCI_DEV(0, 0xd, 0)
#define PMC_DEV PCI_DEV(0, 0xd, 1)
#define SPI_DEV PCI_DEV(0, 0xd, 2)