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authorSubrata Banik <subrata.banik@intel.com>2017-05-19 13:44:14 +0530
committerAaron Durbin <adurbin@chromium.org>2017-06-01 21:48:43 +0200
commitd18b53f45dca75d82bc011e217edad045add23ef (patch)
tree5d3b72c744140c4d7ffea3cc86d95dc87e1fd38c /src/soc/intel/apollolake/include
parentf5f7c84a58c61ff690bf9dd4260280e93353d4fe (diff)
soc/intel/apollolake: Use MCH_BASE_ADDRESS macro for APL
Systemagent common code will use MCH_BASE_ADDRESS macro, hence cleaning current APL code to adhere such changes. Change-Id: Iace1cf786b08221c3955101186509ac5161c3841 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/19793 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc/intel/apollolake/include')
-rw-r--r--src/soc/intel/apollolake/include/soc/iomap.h8
-rw-r--r--src/soc/intel/apollolake/include/soc/systemagent.h5
2 files changed, 6 insertions, 7 deletions
diff --git a/src/soc/intel/apollolake/include/soc/iomap.h b/src/soc/intel/apollolake/include/soc/iomap.h
index eab1273770..0b52095879 100644
--- a/src/soc/intel/apollolake/include/soc/iomap.h
+++ b/src/soc/intel/apollolake/include/soc/iomap.h
@@ -22,15 +22,9 @@
#define P2SB_BAR CONFIG_PCR_BASE_ADDRESS
#define P2SB_SIZE (16 * MiB)
-#define MCH_BASE_ADDR 0xfed10000
+#define MCH_BASE_ADDRESS 0xfed10000
#define MCH_BASE_SIZE (32 * KiB)
-#define P_CR_CORE_DISABLE_MASK_0_0_0_MCHBAR 0x7168
-#define P_CR_BIOS_RESET_CPL_0_0_0_MCHBAR 0x7078
-#define PUNIT_THERMAL_DEVICE_IRQ 0x700C
-#define PUINT_THERMAL_DEVICE_IRQ_VEC_NUMBER 0x18
-#define PUINT_THERMAL_DEVICE_IRQ_LOCK 0x80000000
-
#define ACPI_PMIO_BASE 0x400
#define ACPI_PMIO_SIZE 0x100
#define R_ACPI_PM1_TMR 0x8
diff --git a/src/soc/intel/apollolake/include/soc/systemagent.h b/src/soc/intel/apollolake/include/soc/systemagent.h
index 9944c15197..6b423db840 100644
--- a/src/soc/intel/apollolake/include/soc/systemagent.h
+++ b/src/soc/intel/apollolake/include/soc/systemagent.h
@@ -27,6 +27,11 @@
#define MCH_NUM_IMRS 20
/* RAPL Package Power Limit register under MCHBAR. */
+#define PUNIT_THERMAL_DEVICE_IRQ 0x700C
+#define PUINT_THERMAL_DEVICE_IRQ_VEC_NUMBER 0x18
+#define PUINT_THERMAL_DEVICE_IRQ_LOCK 0x80000000
+#define BIOS_RESET_CPL 0x7078
#define MCHBAR_RAPL_PPL 0x70A8
+#define CORE_DISABLE_MASK 0x7168
#endif /* SOC_APOLLOLAKE_SYSTEMAGENT_H */