summaryrefslogtreecommitdiff
path: root/src/soc/intel/apollolake/include
diff options
context:
space:
mode:
authorFurquan Shaikh <furquan@google.com>2016-06-17 15:50:24 -0700
committerFurquan Shaikh <furquan@google.com>2016-06-21 20:04:33 +0200
commitbae6383607ecf2415206e98c58da47cb10b66f7d (patch)
tree23389296a9962906e3efa901eec3bad1ff7b6362 /src/soc/intel/apollolake/include
parentcad9b631365c0aa3f917455c3dd44edc3e0d21d4 (diff)
intel/apollolake/spi: Add support for reading status reg
spi_read_status reads the status register using hardware sequencing and returns 0 on success and -1 on error. Use spi_read_status to return appropriate value for get_sw_write_protect. BUG=chrome-os-partner:54283 Change-Id: I7650b5c0ab05a8429c2b291f00d4672446d86e03 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/15266 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc/intel/apollolake/include')
-rw-r--r--src/soc/intel/apollolake/include/soc/spi.h7
1 files changed, 7 insertions, 0 deletions
diff --git a/src/soc/intel/apollolake/include/soc/spi.h b/src/soc/intel/apollolake/include/soc/spi.h
index 52ea7709c7..1414a84686 100644
--- a/src/soc/intel/apollolake/include/soc/spi.h
+++ b/src/soc/intel/apollolake/include/soc/spi.h
@@ -59,6 +59,7 @@
#define SPIBAR_HSFSTS_CYCLE_WRITE SPIBAR_HSFSTS_FCYCLE(2)
#define SPIBAR_HSFSTS_CYCLE_4K_ERASE SPIBAR_HSFSTS_FCYCLE(3)
#define SPIBAR_HSFSTS_CYCLE_64K_ERASE SPIBAR_HSFSTS_FCYCLE(4)
+#define SPIBAR_HSFSTS_CYCLE_RD_STATUS SPIBAR_HSFSTS_FCYCLE(8)
/* Bit definitions for PTINX register */
#define SPIBAR_PTINX_COMP_0 (0 << 14)
@@ -68,4 +69,10 @@
#define SPIBAR_PTINX_HORD_JEDEC (2 << 12)
#define SPIBAR_PTINX_IDX_MASK 0xffc
+/*
+ * Reads status register. On success returns 0 and status contains the value
+ * read from the status register. On error returns -1.
+ */
+int spi_read_status(uint8_t *status);
+
#endif