diff options
| author | Aaron Durbin <adurbin@chromium.org> | 2016-06-10 18:04:21 -0500 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2016-06-12 12:52:28 +0200 |
| commit | a554b71e3207556dd563c5253e79ff15a601dc0e (patch) | |
| tree | ddf4291b96d5241fa2e0a4c1d16acef66add85b2 /src/soc/intel/apollolake/include | |
| parent | 7929dd02e68ba52a41c5a8a48b6b7bf8b918677d (diff) | |
soc/intel/apollolake: provide fake PM1 SMI status bit
It appears that PM1 is not wired up to the SMI status register, but
it does definitely cause SMIs to trigger. Therefore, provide a fake
PM1 status bit by checking the power button status when SMI status
is indicating no status as well as the PM1 control indicating that
SCI mode is not enabled.
BUG=chrome-os-partner:54262
TEST=Smashed power button on reef to cause SMI in firmware. No longer
loops infinitely with constant SMIs firing.
Change-Id: I9aa1b5f79b651cbc19a2d3353d9ef65429386889
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/15155
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/soc/intel/apollolake/include')
| -rw-r--r-- | src/soc/intel/apollolake/include/soc/pm.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/soc/intel/apollolake/include/soc/pm.h b/src/soc/intel/apollolake/include/soc/pm.h index c889453f2e..856872ed97 100644 --- a/src/soc/intel/apollolake/include/soc/pm.h +++ b/src/soc/intel/apollolake/include/soc/pm.h @@ -100,6 +100,7 @@ #define MC_SMI_STS 12 #define GPIO_UNLOCK_SMI_STS 11 #define GPIO_SMI_STS 10 +#define FAKE_PM1_SMI_STS 8 #define SWSMI_TMR_SMI_STS 6 #define APM_SMI_STS 5 #define SLP_SMI_STS 4 |