diff options
| author | Duncan Laurie <dlaurie@chromium.org> | 2016-09-19 12:02:54 -0700 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2016-09-21 10:46:14 +0200 |
| commit | a673d1cd2d4d74fdc6f373952f14667f51908f1d (patch) | |
| tree | 40962ef0979455c7895f267d26fc9185b6486187 /src/soc/intel/apollolake/include | |
| parent | 1f6e6813554606bb23481fe64401809ab43bdcc7 (diff) | |
soc/intel/apollolake: Initialize GPEs in bootblock
Initialize the GPEs from mainboard config in bootblock, so they
can be used in verstage to query latched interrupt status.
I still left it called in ramstage just to be sure that the
configuration was not overwritten in FSP stages.
Tested by reading and reporting GPE status in a loop in verstage
and manually triggering an interrupt on EC console.
BUG=chrome-os-partner:53336
Change-Id: Iacd0483e4b3229aca602bb5bb40586eedf35a6ea
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/16670
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc/intel/apollolake/include')
| -rw-r--r-- | src/soc/intel/apollolake/include/soc/pm.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/soc/intel/apollolake/include/soc/pm.h b/src/soc/intel/apollolake/include/soc/pm.h index 2c12c8d28e..dd9e5265a1 100644 --- a/src/soc/intel/apollolake/include/soc/pm.h +++ b/src/soc/intel/apollolake/include/soc/pm.h @@ -206,6 +206,7 @@ void enable_gpe(uint32_t mask); void disable_gpe(uint32_t mask); void disable_all_gpe(void); uintptr_t get_pmc_mmio_bar(void); +void pmc_gpe_init(void); void global_reset_enable(bool enable); void global_reset_lock(void); |