diff options
| author | Aaron Durbin <adurbin@chromium.org> | 2016-08-25 15:42:04 -0500 |
|---|---|---|
| committer | Aaron Durbin <adurbin@chromium.org> | 2016-08-30 03:15:32 +0200 |
| commit | 41a3fa66a0d8a6b134ceb17b8f34520cad7643a4 (patch) | |
| tree | 7e28a0a57b23ec86b10a3ee6d2d8e4699797fffd /src/soc/intel/apollolake/include | |
| parent | a1e39248692e659d0cdf397251a8c138d290d334 (diff) | |
soc/intel/apollolake: add option for SLP_S3_L assertion width
In order to provide time for the S0 rails to discharge one needs
to be able to set the SLP_S3_L assertion width. The hardware default
is 60 microcseconds which is not slow enough on most boards. Therefore
provide a devicetree option for the mainboard to set accordingly
for its needs. An unset value in devicetree results in a conservative
2 second SLP_S3_L duration.
BUG=chrome-os-partner:56581
Change-Id: I6c6df2f7a181746708ab7897249ae82109c55f50
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/16326
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
Diffstat (limited to 'src/soc/intel/apollolake/include')
| -rw-r--r-- | src/soc/intel/apollolake/include/soc/pm.h | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/src/soc/intel/apollolake/include/soc/pm.h b/src/soc/intel/apollolake/include/soc/pm.h index b3da3aa628..3ee7403b9b 100644 --- a/src/soc/intel/apollolake/include/soc/pm.h +++ b/src/soc/intel/apollolake/include/soc/pm.h @@ -151,6 +151,12 @@ #define RPS (1 << 2) #define GEN_PMCON2 0x1024 #define GEN_PMCON3 0x1028 +# define SLP_S3_ASSERT_WIDTH_SHIFT 10 +# define SLP_S3_ASSERT_MASK (0x3 << SLP_S3_ASSERT_WIDTH_SHIFT) +# define SLP_S3_ASSERT_60_USEC 0x0 +# define SLP_S3_ASSERT_1_MSEC 0x1 +# define SLP_S3_ASSERT_50_MSEC 0x2 +# define SLP_S3_ASSERT_2_SEC 0x3 #define ETR 0x1048 # define CF9_LOCK (1 << 31) # define CF9_GLB_RST (1 << 20) |