diff options
| author | Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> | 2016-08-23 11:20:20 +0530 |
|---|---|---|
| committer | Aaron Durbin <adurbin@chromium.org> | 2016-09-14 22:18:42 +0200 |
| commit | 35240ebe3c543e3ea416765d980ba8774d14754d (patch) | |
| tree | 8277ec33ce901dfb4fd5ae9541b9c3e8f88cf459 /src/soc/intel/apollolake/include | |
| parent | 8cdeef1c0d1e6453a027642d2504e58ab9ac7152 (diff) | |
soc/intel/apollolake: Update PL1 value in RAPL MMIO register
Due to an incorrect value set for the power limit PL1, the
system is not able to leverage full TDP capacity. FSP code
sets the PL1 value as 6W in RAPL MMIO register based on
fused soc tdp value. This RAPL MMIO register is a physically
separate instance from RAPL MSR register. This patch sets
PL1 value to 15W in RAPL MMIO register.
BUG=chrome-os-partner:56524
TEST=Built, booted on reef and verifed the package power
with heavy workload.
Change-Id: Ib344247cd8d98ccce7c403e778cd87c13f168ce0
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/16595
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc/intel/apollolake/include')
| -rw-r--r-- | src/soc/intel/apollolake/include/soc/cpu.h | 1 | ||||
| -rw-r--r-- | src/soc/intel/apollolake/include/soc/northbridge.h | 2 |
2 files changed, 3 insertions, 0 deletions
diff --git a/src/soc/intel/apollolake/include/soc/cpu.h b/src/soc/intel/apollolake/include/soc/cpu.h index 8887c17e81..22412aff2d 100644 --- a/src/soc/intel/apollolake/include/soc/cpu.h +++ b/src/soc/intel/apollolake/include/soc/cpu.h @@ -38,6 +38,7 @@ void apollolake_init_cpus(struct device *dev); #define PREFETCH_L1_DISABLE (1 << 0) #define PREFETCH_L2_DISABLE (1 << 2) +#define MSR_PKG_POWER_SKU_UNIT 0x606 #define MSR_L2_QOS_MASK(reg) (0xd10 + reg) #define MSR_IA32_PQR_ASSOC 0xc8f diff --git a/src/soc/intel/apollolake/include/soc/northbridge.h b/src/soc/intel/apollolake/include/soc/northbridge.h index 0f616747c1..04e369e7e8 100644 --- a/src/soc/intel/apollolake/include/soc/northbridge.h +++ b/src/soc/intel/apollolake/include/soc/northbridge.h @@ -34,5 +34,7 @@ #define MCH_IMR_PITCH 0x20 #define MCH_NUM_IMRS 20 +/* RAPL Package Power Limit register under MCHBAR. */ +#define MCHBAR_RAPL_PPL 0x70A8 #endif /* _SOC_APOLLOLAKE_NORTHBRIDGE_H_ */ |