soc/intel/apollolake: Use common gpio for apollolake

No regression observed on a APL platform

Change-Id: I0fcc22df5eaec014f3b89755415f051b05aa554a
Signed-off-by: Hannah Williams <hannah.williams@intel.com>
Reviewed-on: https://review.coreboot.org/19949
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

2 files changed, 29 insertions, 265 deletions

diff --git a/src/soc/intel/apollolake/include/soc/gpio.h b/src/soc/intel/apollolake/include/soc/gpio.h
index 85fc759bcd..a4d766beba 100644
--- a/src/soc/intel/apollolake/include/soc/gpio.h
+++ b/src/soc/intel/apollolake/include/soc/gpio.h
@@ -1,8 +1,7 @@
 /*
  * This file is part of the coreboot project.
  *
- * Copyright (C) 2015 Intel Corp.
- * (Written by Alexandru Gagniuc <alexandrux.gagniuc@intel.com> for Intel Corp.)
+ * Copyright (C) 2017 Intel Corp.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -15,170 +14,10 @@
  * GNU General Public License for more details.
  */
 
-#ifndef _SOC_APOLLOLAKE_GPIO_H_
-#define _SOC_APOLLOLAKE_GPIO_H_
+#ifndef _SOC_APL_GPIO_H_
+#define _SOC_APL_GPIO_H_
 
-#include <soc/gpio_defs.h>
-/* __ACPI__ guard is needed to ignore below code in ACPI/ASL compilation */
-#ifndef __ACPI__
-#include <types.h>
-
-typedef uint32_t gpio_t;
-
-/*
- * Structure to represent GPI status for GPE and SMI. Use helper
- * functions for interrogating particular GPIs. Here the number of
- * array elements is total number of groups that can be present in all
- * the communities.
- */
-struct gpi_status {
-	uint32_t grp[NUM_GPI_STATUS_REGS];
-};
-
-/*
- * Clear GPI SMI status and fill in the structure representing enabled
- * and set status.
- */
-void gpi_clear_get_smi_status(struct gpi_status *sts);
-
-/* Return 1 if gpio is set in the gpi_status struct. Otherwise 0. */
-int gpi_status_get(const struct gpi_status *sts, gpio_t gpi);
-
-#define PAD_FUNC(value)		PAD_CFG0_MODE_##value
-#define PAD_RESET(value)	PAD_CFG0_RESET_##value
-#define PAD_PULL(value)		PAD_CFG1_PULL_##value
-#define PAD_IOSSTATE(value)	PAD_CFG1_IOSSTATE_##value
-#define PAD_IOSTERM(value)	PAD_CFG1_IOSTERM_##value
-#define PAD_IRQ_CFG(route, trig, inv) \
-				(PAD_CFG0_ROUTE_##route | \
-				PAD_CFG0_TRIG_##trig | \
-				(PAD_CFG0_RX_POL_##inv))
-
-#define _PAD_CFG_STRUCT(__pad, __config0, __config1)	\
-	{					\
-		.pad = __pad,			\
-		.config0 = __config0,		\
-		.config1 = __config1,		\
-	}
-
-/* Native function configuration */
-#define PAD_CFG_NF(pad, pull, rst, func) \
-	PAD_CFG_NF_IOSSTATE(pad, pull, rst, func, TxLASTRxE)
-
-/* Native function configuration for standby state */
-#define PAD_CFG_NF_IOSSTATE(pad, pull, rst, func, iosstate) \
-	PAD_CFG_NF_IOSSTATE_IOSTERM(pad,pull, rst, func, iosstate, SAME)
-
-#define PAD_CFG_NF_IOSSTATE_IOSTERM(pad, pull, rst, func, iosstate, iosterm) \
-	_PAD_CFG_STRUCT(pad, PAD_RESET(rst) | PAD_FUNC(func), PAD_PULL(pull) | \
-		PAD_IOSSTATE(iosstate) | PAD_IOSTERM(iosterm))
-
-/* General purpose output, no pullup/down. */
-#define PAD_CFG_GPO(pad, val, rst)	\
-	_PAD_CFG_STRUCT(pad,		\
-		PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_RX_DISABLE | !!val, \
-		PAD_PULL(NONE) | PAD_IOSSTATE(TxLASTRxE))
-
-/* General purpose input */
-#define PAD_CFG_GPI(pad, pull, rst) \
-	_PAD_CFG_STRUCT(pad,		\
-		PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE, \
-		PAD_PULL(pull) | PAD_IOSSTATE(TxLASTRxE))
-
-/* General purpose input. The following macro sets the
- * Host Software Pad Ownership to GPIO Driver mode.
- */
-#define PAD_CFG_GPI_GPIO_DRIVER(pad, pull, rst) \
-	_PAD_CFG_STRUCT(pad,		\
-		PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE, \
-		PAD_PULL(pull) | PAD_CFG1_GPIO_DRIVER | PAD_IOSSTATE(TxLASTRxE))
-
-/* No Connect configuration for unused pad.
- * NC should be GPI with Term as PU20K, PD20K, NONE depending upon default Term
- */
-#define PAD_NC(pad, pull)	PAD_CFG_GPI(pad, pull, DEEP)
-
-/* General purpose input, routed to APIC */
-#define PAD_CFG_GPI_APIC(pad, pull, rst, trig, inv) \
-	_PAD_CFG_STRUCT(pad,		\
-		PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE | \
-		PAD_IRQ_CFG(IOAPIC, trig, inv), PAD_PULL(pull) | \
-		PAD_IOSSTATE(TxLASTRxE))
-
-/*
- * The following APIC macros assume the APIC will handle the filtering
- * on its own end. One just needs to pass an active high message into the
- * ITSS.
- */
-#define PAD_CFG_GPI_APIC_LOW(pad, pull, rst) \
-	PAD_CFG_GPI_APIC(pad, pull, rst, LEVEL, INVERT)
-
-#define PAD_CFG_GPI_APIC_HIGH(pad, pull, rst) \
-	PAD_CFG_GPI_APIC(pad, pull, rst, LEVEL, NONE)
-
-/* General purpose input, routed to SMI */
-#define PAD_CFG_GPI_SMI(pad, pull, rst, trig, inv) \
-	_PAD_CFG_STRUCT(pad,		\
-		PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE | \
-		PAD_IRQ_CFG(SMI, trig, inv), PAD_PULL(pull) | \
-		PAD_IOSSTATE(TxLASTRxE))
-
-#define PAD_CFG_GPI_SMI_LOW(pad, pull, rst, trig) \
-	PAD_CFG_GPI_SMI(pad, pull, rst, trig, INVERT)
-
-#define PAD_CFG_GPI_SMI_HIGH(pad, pull, rst, trig) \
-	PAD_CFG_GPI_SMI(pad, pull, rst, trig, NONE)
-
-/* General purpose input, routed to SCI */
-#define PAD_CFG_GPI_SCI(pad, pull, rst, trig, inv) \
-	_PAD_CFG_STRUCT(pad,		\
-		PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE | \
-		PAD_IRQ_CFG(SCI, trig, inv), PAD_PULL(pull) | \
-		PAD_IOSSTATE(TxLASTRxE))
-
-#define PAD_CFG_GPI_SCI_LOW(pad, pull, rst, trig) \
-	PAD_CFG_GPI_SCI(pad, pull, rst, trig, INVERT)
-
-#define PAD_CFG_GPI_SCI_HIGH(pad, pull, rst, trig) \
-	PAD_CFG_GPI_SCI(pad, pull, rst, trig, NONE)
-
-/* General purpose input, routed to NMI */
-#define PAD_CFG_GPI_NMI(pad, pull, rst, trig, inv) \
-	_PAD_CFG_STRUCT(pad,		\
-		PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE | \
-		PAD_IRQ_CFG(NMI, trig, inv), PAD_PULL(pull) | \
-		PAD_IOSSTATE(TxLASTRxE))
-
-struct pad_config {
-	uint32_t config0;
-	uint16_t config1;
-	uint16_t pad;
-};
-
-/*
- * Configuration for raw pads. Some pads are designated as only special function
- * pins, and don't have an associated GPIO number, so we need to expose the raw
- * pad configuration functionality.
- */
-void gpio_configure_pad(const struct pad_config *cfg);
-void gpio_configure_pads(const struct pad_config *cfg, size_t num_pads);
-
-/* Calculate GPIO DW0 address */
-void *gpio_dwx_address(const uint16_t pad);
-
-/* Get the port id of given pad */
-uint8_t gpio_get_pad_portid(const uint16_t pad);
-
-/*
- * Set the GPIO groups for the GPE blocks. The values from PMC register GPE_CFG
- * are passed which is then mapped to proper groups for MISCCFG. This basically
- * sets the MISCCFG register bits:
- *  dw0 = gpe0_route[11:8]. This is ACPI GPE0b.
- *  dw1 = gpe0_route[15:12]. This is ACPI GPE0c.
- *  dw2 = gpe0_route[19:16]. This is ACPI GPE0d.
- */
-void gpio_route_gpe(uint8_t gpe0b, uint8_t gpe0c, uint8_t gpe0d);
-
-#endif /* __ACPI__ */
-
-#endif /* _SOC_APOLLOLAKE_GPIO_H_ */
+#include <soc/gpio_apl.h>
+#include <intelblocks/gpio.h> /* intelblocks/gpio.h depends on definitions in
+				soc/gpio_apl.h */
+#endif
diff --git a/src/soc/intel/apollolake/include/soc/gpio_defs.h b/src/soc/intel/apollolake/include/soc/gpio_apl.h
index 938d4148f1..67c8a756b6 100644
--- a/src/soc/intel/apollolake/include/soc/gpio_defs.h
+++ b/src/soc/intel/apollolake/include/soc/gpio_apl.h
@@ -6,7 +6,7 @@
  *
  * This file is part of the coreboot project.
  *
- * Copyright (C) 2015 Intel Corp.
+ * Copyright (C) 2015 - 2017 Intel Corp.
  * (Written by Alexandru Gagniuc <alexandrux.gagniuc@intel.com> for Intel Corp.)
  *
  * This program is free software; you can redistribute it and/or modify
@@ -20,8 +20,8 @@
  * GNU General Public License for more details.
  */
 
-#ifndef _SOC_APOLLOLAKE_GPIO_DEFS_H_
-#define _SOC_APOLLOLAKE_GPIO_DEFS_H_
+#ifndef _SOC_APOLLOLAKE_GPIO_H_
+#define _SOC_APOLLOLAKE_GPIO_H_
 
 /*
  * Miscellaneous Configuration register(MISCCFG).These are community specific
@@ -40,103 +40,19 @@
 
 #define GPIO_MAX_NUM_PER_GROUP	32
 
-#define MISCCFG_GPE0_DW0_SHIFT 8
-#define MISCCFG_GPE0_DW0_MASK (0xf << MISCCFG_GPE0_DW0_SHIFT)
-#define MISCCFG_GPE0_DW1_SHIFT 12
-#define MISCCFG_GPE0_DW1_MASK (0xf << MISCCFG_GPE0_DW1_SHIFT)
-#define MISCCFG_GPE0_DW2_SHIFT 16
-#define MISCCFG_GPE0_DW2_MASK (0xf << MISCCFG_GPE0_DW2_SHIFT)
 
 /* Host Software Pad Ownership Register.
  * The pins in the community are divided into 3 groups :
  * GPIO 0 ~ 31, GPIO 32 ~ 63, GPIO 64 ~ 95
  */
-#define HOSTSW_OWN_REG_BASE		0x80
-
-#define PAD_CFG0_TX_STATE		(1 << 0)
-#define PAD_CFG0_RX_STATE		(1 << 1)
-#define PAD_CFG0_TX_DISABLE		(1 << 8)
-#define PAD_CFG0_RX_DISABLE		(1 << 9)
-#define PAD_CFG0_MODE_MASK		(7 << 10)
-#define  PAD_CFG0_MODE_GPIO		(0 << 10)
-#define  PAD_CFG0_MODE_FUNC(x)		((x) << 10)
-#define  PAD_CFG0_MODE_NF1		(1 << 10)
-#define  PAD_CFG0_MODE_NF2		(2 << 10)
-#define  PAD_CFG0_MODE_NF3		(3 << 10)
-#define  PAD_CFG0_MODE_NF4		(4 << 10)
-#define  PAD_CFG0_MODE_NF5		(5 << 10)
-#define PAD_CFG0_ROUTE_NMI		(1 << 17)
-#define PAD_CFG0_ROUTE_SMI		(1 << 18)
-#define PAD_CFG0_ROUTE_SCI		(1 << 19)
-#define PAD_CFG0_ROUTE_IOAPIC		(1 << 20)
-#define PAD_CFG0_RX_POL_INVERT		(1 << 23)
-#define PAD_CFG0_RX_POL_NONE		(0 << 23)
-
-#define PAD_CFG0_TRIG_MASK		(3 << 25)
-#define  PAD_CFG0_TRIG_LEVEL		(0 << 25)
-#define  PAD_CFG0_TRIG_EDGE_SINGLE	(1 << 25) /* controlled by RX_INVERT*/
-#define  PAD_CFG0_TRIG_OFF		(2 << 25)
-#define  PAD_CFG0_TRIG_EDGE_BOTH	(3 << 25)
-#define PAD_CFG0_RESET_MASK		(3 << 30)
-#define  PAD_CFG0_RESET_PWROK		(0 << 30)
-#define  PAD_CFG0_RESET_DEEP		(1 << 30)
-#define  PAD_CFG0_RESET_PLTRST		(2 << 30)
-#define  PAD_CFG0_RESET_RSMRST		(3 << 30)
-
-/* Use the fourth bit in IntSel field to indicate gpio
- * ownership. This field is RO and hence not used during
- * gpio configuration.
- */
-#define PAD_CFG1_GPIO_DRIVER		(0x1 << 4)
-#define PAD_CFG1_IRQ_MASK		(0xff << 0)
-#define PAD_CFG1_PULL_MASK		(0xf << 10)
-#define  PAD_CFG1_PULL_NONE		(0x0 << 10)
-#define  PAD_CFG1_PULL_DN_5K		(0x2 << 10)
-#define  PAD_CFG1_PULL_DN_20K		(0x4 << 10)
-#define  PAD_CFG1_PULL_UP_1K		(0x9 << 10)
-#define  PAD_CFG1_PULL_UP_5K		(0xa << 10)
-#define  PAD_CFG1_PULL_UP_2K		(0xb << 10)
-#define  PAD_CFG1_PULL_UP_20K		(0xc << 10)
-#define  PAD_CFG1_PULL_UP_667		(0xd << 10)
-#define  PAD_CFG1_PULL_NATIVE		(0xf << 10)
-/* Tx enabled driving last value driven, Rx enabled */
-#define PAD_CFG1_IOSSTATE_TxLASTRxE	(0x0 << 0)
-/* Tx enabled driving 0, Rx disabled and Rx driving 0 back to its controller
- * internally */
-#define PAD_CFG1_IOSSTATE_Tx0RxDCRx0	(0x1 << 0)
-/* Tx enabled driving 0, Rx disabled and Rx driving 1 back to its controller
- * internally */
-#define PAD_CFG1_IOSSTATE_Tx0RXDCRx1	(0x2 << 0)
-/* Tx enabled driving 1, Rx disabled and Rx driving 0 back to its controller
- * internally */
-#define PAD_CFG1_IOSSTATE_Tx1RXDCRx0	(0x3 << 0)
-/* Tx enabled driving 1, Rx disabled and Rx driving 1 back to its controller
- * internally */
-#define PAD_CFG1_IOSSTATE_Tx1RxDCRx1	(0x4 << 0)
-/* Tx enabled driving 0, Rx enabled */
-#define PAD_CFG1_IOSSTATE_Tx0RxE	(0x5 << 0)
-/* Tx enabled driving 1, Rx enabled */
-#define PAD_CFG1_IOSSTATE_Tx1RxE	(0x6 << 0)
-/* Hi-Z, Rx driving 0 back to its controller internally */
-#define PAD_CFG1_IOSSTATE_HIZCRx0	(0x7 << 0)
-/* Hi-Z, Rx driving 1 back to its controller internally */
-#define PAD_CFG1_IOSSTATE_HIZCRx1	(0x8 << 0)
-#define PAD_CFG1_IOSSTATE_TxDRxE	(0x9 << 0) /* Tx disabled, Rx enabled */
-#define PAD_CFG1_IOSSTATE_IGNORE	(0xf << 0) /* Ignore Iostandby */
-#define PAD_CFG1_IOSSTATE_MASK		0xf /* mask to extract Iostandby bits */
-#define PAD_CFG1_IOSSTATE_SHIFT	14 /* set Iostandby bits [17:14] */
-#define PAD_CFG1_IOSTERM_SAME		(0x0 << 8) /* Same as functional mode */
-#define PAD_CFG1_IOSTERM_DISPUPD	(0x1 << 8) /* Disable Pull-up/Pull-down */
-#define PAD_CFG1_IOSTERM_ENPD		(0x2 << 8) /* Enable Pull-down */
-#define PAD_CFG1_IOSTERM_ENPU		(0x3 << 8) /* Enable Pull-up */
+#define HOSTSW_OWN_REG_0		0x80
 
 #define PAD_CFG_BASE			0x500
-#define PAD_CFG_OFFSET(pad)		(PAD_CFG_BASE + ((pad) * 8))
+
+#define GPI_INT_EN_0			0x110
 
 #define GPI_SMI_STS_0			0x140
 #define GPI_SMI_EN_0			0x150
-#define GPI_SMI_STS_OFFSET(group)	(GPI_SMI_STS_0 + ((group) * 4))
-#define GPI_SMI_EN_OFFSET(group)	(GPI_SMI_EN_0 + ((group) * 4))
 
 #define NUM_N_PADS			(PAD_N(SVID0_CLK) + 1)
 #define NUM_NW_PADS			(PAD_NW(GPIO_123) + 1)
@@ -432,13 +348,21 @@
 #define GPIO_COMM_W_NAME		"INT3452:02"
 #define GPIO_COMM_SW_NAME		"INT3452:03"
 
-/* Default configurations */
-#define PAD_CFG0_DEFAULT_FUNC(x)	(PAD_CFG0_RESET_DEEP \
-					| PAD_CFG0_MODE_FUNC(x))
-#define PAD_CFG0_DEFAULT_NATIVE		PAD_CFG0_DEFAULT_FUNC(1)
+/* Following is used in gpio asl */
+#define GPIO_COMM_NAME			"INT3452"
+#define GPIO_COMM_0_DESC	\
+	"General Purpose Input/Output (GPIO) Controller - North"
+#define GPIO_COMM_1_DESC	\
+	"General Purpose Input/Output (GPIO) Controller - Northwest"
+#define GPIO_COMM_2_DESC	\
+	"General Purpose Input/Output (GPIO) Controller - West"
+#define GPIO_COMM_3_DESC	\
+	"General Purpose Input/Output (GPIO) Controller - Southwest"
 
-#define PAD_CFG1_DEFAULT_PULLUP		PAD_CFG1_PULL_UP_20K
-#define PAD_CFG1_DEFAULT_NATIVE		PAD_CFG1_PULL_NATIVE
+#define GPIO_COMM0_PID			PID_GPIO_N
+#define GPIO_COMM1_PID			PID_GPIO_NW
+#define GPIO_COMM2_PID			PID_GPIO_W
+#define GPIO_COMM3_PID			PID_GPIO_SW
 
 /*
  * IOxAPIC IRQs for the GPIOs, overlap is expected as we encourage to use
@@ -554,4 +478,5 @@
 #define GPIO_72_IRQ			0x65
 #define GPIO_73_IRQ			0x66
 
-#endif /* _SOC_APOLLOLAKE_GPIO_DEFS_H_ */
+#define GPIO_NUM_PAD_CFG_REGS   2 /* DW0, DW1 */
+#endif /* _SOC_APOLLOLAKE_GPIO_H_ */