diff options
| author | Aaron Durbin <adurbin@chromium.org> | 2016-10-25 10:14:32 -0500 |
|---|---|---|
| committer | Aaron Durbin <adurbin@chromium.org> | 2016-10-25 19:27:50 +0200 |
| commit | 06590a20142249ef11e306dc8f4f3469e4847b5a (patch) | |
| tree | d4c3ced4808ee6ce9768c9d01021d98b1c17b61b /src/soc/intel/apollolake/include | |
| parent | 79daac98903360db656c49f0078a2bd1744ca25b (diff) | |
Revert "soc/apollolake: Add soc core init"
This reverts commit a52f883b100f3229dd4d86c81c08781993861f73
(https://review.coreboot.org/16587).
The above commit caused another sever kernel boot regression upwards
of 2 minutes to get through kernel init on quad core systems.
BUG=chrome-os-partner:58994
Change-Id: Id4abc332bf2266e3b3b7be714371ce9cf329bcd9
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/17121
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
Diffstat (limited to 'src/soc/intel/apollolake/include')
| -rw-r--r-- | src/soc/intel/apollolake/include/soc/cpu.h | 13 | ||||
| -rw-r--r-- | src/soc/intel/apollolake/include/soc/iomap.h | 7 |
2 files changed, 1 insertions, 19 deletions
diff --git a/src/soc/intel/apollolake/include/soc/cpu.h b/src/soc/intel/apollolake/include/soc/cpu.h index e94972d90b..bffe4bcd8d 100644 --- a/src/soc/intel/apollolake/include/soc/cpu.h +++ b/src/soc/intel/apollolake/include/soc/cpu.h @@ -54,19 +54,6 @@ void apollolake_init_cpus(struct device *dev); */ #define MB_POWER_LIMIT1_TIME_DEFAULT 0x6e -/* Set MSR_PMG_CST_CONFIG_CONTROL[3:0] for Package C-State limit */ -#define PKG_C_STATE_LIMIT_C2_MASK 0x2 -/* Set MSR_PMG_CST_CONFIG_CONTROL[7:4] for Core C-State limit*/ -#define CORE_C_STATE_LIMIT_C10_MASK 0x70 -/* Set MSR_PMG_CST_CONFIG_CONTROL[10] to IO redirect to MWAIT */ -#define IO_MWAIT_REDIRECT_MASK 0x400 -/* Set MSR_PMG_CST_CONFIG_CONTROL[15] to lock CST_CFG [0-15] bits */ -#define CST_CFG_LOCK_MASK 0x8000 - -#define MSR_PMG_CST_CONFIG_CONTROL 0xe2 -#define MSR_PMG_IO_CAPTURE_BASE 0xe4 -#define MSR_POWER_CTL 0x1fc - #define MSR_L2_QOS_MASK(reg) (0xd10 + reg) #define MSR_IA32_PQR_ASSOC 0xc8f /* MSR bits 33:32 encode slot number 0-3 */ diff --git a/src/soc/intel/apollolake/include/soc/iomap.h b/src/soc/intel/apollolake/include/soc/iomap.h index d5d8f878ef..621b0a6808 100644 --- a/src/soc/intel/apollolake/include/soc/iomap.h +++ b/src/soc/intel/apollolake/include/soc/iomap.h @@ -27,12 +27,7 @@ #define ACPI_PMIO_BASE 0x400 #define ACPI_PMIO_SIZE 0x100 -#define R_ACPI_PM1_TMR 0x8 - -/* CST Range (R/W) IO port block size */ -#define PMG_IO_BASE_CST_RNG_BLK_SIZE 0x5 -/* ACPI PMIO Offset to C-state register*/ -#define ACPI_PMIO_CST_REG (ACPI_PMIO_BASE + 0x14) +#define R_ACPI_PM1_TMR 0x8 /* Accesses to these BARs are hardcoded in FSP */ #define PMC_BAR0 0xfe042000 |