diff options
| author | Werner Zeh <werner.zeh@siemens.com> | 2022-05-19 10:01:37 +0200 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-05-24 13:45:15 +0000 |
| commit | 859305d45762d8499b4100765d3a7bd954038c73 (patch) | |
| tree | 243eac3ff3a09f27f5d9f43c561562266f2d3db9 /src/soc/intel/apollolake/include | |
| parent | 5c808e03e2d80edd9ecd6a2a9268152b477940b6 (diff) | |
soc/intel/apollolake: Measure bootblock from IFWI
On Apollo Lake the bootblock is stitched into the IBBL IFWI region at
build time. At execution time TXE loads this IBBL into a shared SRAM
(which is read-only in this phase) and maps it at 4 GiB - 32 KiB. Then
the CPU starts to operate from this shared SRAM as it were flash space.
In order to provide a reliable CRTM init, the real executed bootblock
code needs to be measured into TPM if VBOOT is selected. This patch adds
the needed code to do this.
Change-Id: Ifb3f798de638a85029ebfe0d1b65770029297db3
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64493
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Diffstat (limited to 'src/soc/intel/apollolake/include')
| -rw-r--r-- | src/soc/intel/apollolake/include/soc/iomap.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/soc/intel/apollolake/include/soc/iomap.h b/src/soc/intel/apollolake/include/soc/iomap.h index 209e1c2674..5f1b014722 100644 --- a/src/soc/intel/apollolake/include/soc/iomap.h +++ b/src/soc/intel/apollolake/include/soc/iomap.h @@ -31,6 +31,8 @@ #define SRAM_SIZE_0 (8 * KiB) #define SRAM_BASE_2 0xfe902000 #define SRAM_SIZE_2 (4 * KiB) +#define SHARED_SRAM_BASE 0xfffe0000 +#define SHARED_SRAM_SIZE (128 * KiB) #define HECI1_BASE_ADDRESS 0xfed1a000 #define PSF3_BASE_ADDRESS 0x1e00 |