summaryrefslogtreecommitdiff
path: root/src/soc/intel/apollolake/include
diff options
context:
space:
mode:
authorSubrata Banik <subrata.banik@intel.com>2018-05-07 17:13:40 +0530
committerSubrata Banik <subrata.banik@intel.com>2018-06-28 08:35:29 +0000
commit7837c203d615fce03c6d89d99ba9a746619e49d4 (patch)
treeba3626a10a35bd99108228611b18e7f76b7abd02 /src/soc/intel/apollolake/include
parent210b351df3cc070f103feb01a40be9811af87906 (diff)
soc/intel/common/block: Move p2sb common functions into block/p2sb
This patch cleans soc/intel/{apollolake/cannonlake/skylake} by moving common soc code into common/block/p2sb. BUG=b:78109109 BRANCH=none TEST=Build and boot KBL/CNL/APL platform. Change-Id: Ie9fd933d155b3fcd0d616b41cdf042cefe2c649a Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/26132 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/soc/intel/apollolake/include')
-rw-r--r--src/soc/intel/apollolake/include/soc/p2sb.h25
1 files changed, 25 insertions, 0 deletions
diff --git a/src/soc/intel/apollolake/include/soc/p2sb.h b/src/soc/intel/apollolake/include/soc/p2sb.h
new file mode 100644
index 0000000000..01ba7ffd24
--- /dev/null
+++ b/src/soc/intel/apollolake/include/soc/p2sb.h
@@ -0,0 +1,25 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2018 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _SOC_P2SB_H_
+#define _SOC_P2SB_H_
+
+/* PCI config space registers */
+#define HPTC_OFFSET 0x60
+#define HPTC_ADDR_ENABLE_BIT (1 << 7)
+
+#define PCH_P2SB_EPMASK0 0xB0
+
+#endif /* _SOC_P2SB_H_ */