diff options
| author | Brandon Breitenstein <brandon.breitenstein@intel.com> | 2016-07-18 15:14:12 -0700 |
|---|---|---|
| committer | Aaron Durbin <adurbin@chromium.org> | 2016-08-25 23:51:27 +0200 |
| commit | 3b0e761dd5008b9b87d207f9c7d7571fc880a523 (patch) | |
| tree | 4289c2368848b428ddd1da9cc247650bc75fcd2f /src/soc/intel/apollolake/include | |
| parent | de9fed4c2a6014b25042899e199cfe9a6115b52e (diff) | |
soc/intel/apollolake: Enable ELOG
Add in the base for ELOG for APL. Some PM events still need to be
added but the basic events are logged here. This enables the
basic functionality of ELOG for Apollolake.
BUG=chrome-os-partner:55473
BRANCH=none
TEST=Verified image boots on Amenia
Change-Id: I8682293e5a55b3efb5fdd9f1be1f3e4bf8d0757c
Signed-off-by: Brandon Breitenstein <brandon.breitenstein@intel.com>
Reviewed-on: https://review.coreboot.org/15937
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
Diffstat (limited to 'src/soc/intel/apollolake/include')
| -rw-r--r-- | src/soc/intel/apollolake/include/soc/pm.h | 34 |
1 files changed, 29 insertions, 5 deletions
diff --git a/src/soc/intel/apollolake/include/soc/pm.h b/src/soc/intel/apollolake/include/soc/pm.h index 7eb593002e..b3da3aa628 100644 --- a/src/soc/intel/apollolake/include/soc/pm.h +++ b/src/soc/intel/apollolake/include/soc/pm.h @@ -25,16 +25,17 @@ #define PM1_STS 0x00 #define WAK_STS (1 << 15) +#define PCIEXPWAK_STS (1 << 14) +#define PRBTNOR_STS (1 << 11) #define RTC_STS (1 << 10) #define PWRBTN_STS (1 << 8) +#define GBL_STS (1 << 5) #define PM1_EN 0x02 #define PCIEXPWAK_DIS (1 << 14) -#define USB_WAKE_EN (1 << 13) #define RTC_EN (1 << 10) #define PWRBTN_EN (1 << 8) #define GBL_EN (1 << 5) -#define TMROF_EN (1 << 0) #define PM1_CNT 0x04 #define SCI_EN (1 << 0) @@ -113,8 +114,30 @@ #define GPE0_REG_MAX 4 #define GPE0_REG_SIZE 32 #define GPE0_STS(x) (0x20 + (x * 4)) +#define GPE0_A 0 +#define GPE0_B 1 +#define GPE0_C 2 +#define GPE0_D 3 +#define SATA_PME_STS (1 << 17) +#define SMB_WAK_STS (1 << 16) +#define AVS_PME_STS (1 << 14) +#define XHCI_PME_STS (1 << 13) +#define XDCI_PME_STS (1 << 12) +#define CSE_PME_STS (1 << 11) +#define BATLOW_STS (1 << 10) +#define PCIE_GPE_STS (1 << 9) +#define SWGPE_STS (1 << 2) #define GPE0_EN(x) (0x30 + (x * 4)) +#define SATA_PME_EN (1 << 17) +#define SMB_WAK_EN (1 << 16) +#define AVS_PME_EN (1 << 14) #define PME_B0_EN (1 << 13) +#define XDCI_PME_EN (1 << 12) +#define CSE_PME_EN (1 << 11) +#define BATLOW_EN (1 << 10) +#define PCIE_GPE_EN (1 << 9) +#define SWGPE_EN (1 << 2) + /* * Enables the setting of the GPIO_TIER1_SCI_STS bit to generate a wake event * and/or an SCI or SMI#. @@ -124,10 +147,9 @@ /* Memory mapped IO registers behind PMC_BASE_ADDRESS */ #define PRSTS 0x1000 #define GEN_PMCON1 0x1020 -# define PWR_FLR (1 << 16) -# define SUS_PWR_FLR (1 << 14) +#define SRS (1 << 20) +#define RPS (1 << 2) #define GEN_PMCON2 0x1024 -# define RPS (1 << 2) #define GEN_PMCON3 0x1028 #define ETR 0x1048 # define CF9_LOCK (1 << 31) @@ -188,4 +210,6 @@ uintptr_t get_pmc_mmio_bar(void); void global_reset_enable(bool enable); void global_reset_lock(void); +void pch_log_state(void); + #endif |