soc/intel: deduplicate ACPI timer emulation

The code for enabling ACPI timer emulation is the same for the SoCs
SKL, CNL, ICL, TGL, JSL and EHL. Deduplicate it by moving it to
common code.

APL differs in not having the delay settings. However, the bits are
marked as "spare" and BWG mentions there are no "reserved bit checks
done". Thus, we can write them unconditionally without any effect.

Note: The ACPI timer emulation can only be used by SoCs with microcode
supporting CTC (Common Timer Copy) / ACPI timer emulation.

Change-Id: Ied4b312b6d53e80e71c55f4d1ca78a8cb2799793
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45951
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>

1 files changed, 0 insertions, 2 deletions

diff --git a/src/soc/intel/apollolake/include/soc/pm.h b/src/soc/intel/apollolake/include/soc/pm.h
index aaf62583e6..748f76adba 100644
--- a/src/soc/intel/apollolake/include/soc/pm.h
+++ b/src/soc/intel/apollolake/include/soc/pm.h
@@ -234,8 +234,6 @@ struct chipset_power_state {
 
 void pch_log_state(void);
 
-void enable_pm_timer_emulation(void);
-
 /* STM Support */
 uint16_t get_pmbase(void);