soc/intel/apollolake: Use common PCR module

This patch use common PCR library to perform CRRd and CRWr operation
using Port Ids, define inside soc/pcr_ids.h

Change-Id: Iacbf58dbd55bf3915676d875fcb484362d357a44
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/18673
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

4 files changed, 31 insertions, 50 deletions

diff --git a/src/soc/intel/apollolake/include/soc/gpio_defs.h b/src/soc/intel/apollolake/include/soc/gpio_defs.h
index 2fdf10f7f7..1694d10949 100644
--- a/src/soc/intel/apollolake/include/soc/gpio_defs.h
+++ b/src/soc/intel/apollolake/include/soc/gpio_defs.h
@@ -129,13 +129,6 @@
 #define PAD_CFG_BASE			0x500
 #define PAD_CFG_OFFSET(pad)		(PAD_CFG_BASE + ((pad) * 8))
 
-/* IOSF port numbers for GPIO comminuties*/
-#define GPIO_SW			0xc0
-#define GPIO_S			0xc2
-#define GPIO_NW			0xc4
-#define GPIO_N			0xc5
-#define GPIO_W			0xc7
-
 #define GPI_SMI_STS_0			0x140
 #define GPI_SMI_EN_0			0x150
 #define GPI_SMI_STS_OFFSET(group)	(GPI_SMI_STS_0 + ((group) * 4))
diff --git a/src/soc/intel/apollolake/include/soc/iomap.h b/src/soc/intel/apollolake/include/soc/iomap.h
index 3c94d1b608..eab1273770 100644
--- a/src/soc/intel/apollolake/include/soc/iomap.h
+++ b/src/soc/intel/apollolake/include/soc/iomap.h
@@ -20,7 +20,7 @@
 
 #include <commonlib/helpers.h>
 
-#define P2SB_BAR			CONFIG_IOSF_BASE_ADDRESS
+#define P2SB_BAR			CONFIG_PCR_BASE_ADDRESS
 #define P2SB_SIZE			(16 * MiB)
 #define MCH_BASE_ADDR			0xfed10000
 #define MCH_BASE_SIZE			(32 * KiB)
diff --git a/src/soc/intel/apollolake/include/soc/iosf.h b/src/soc/intel/apollolake/include/soc/iosf.h
deleted file mode 100644
index 3c96c581ac..0000000000
--- a/src/soc/intel/apollolake/include/soc/iosf.h
+++ /dev/null
@@ -1,42 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2015 Intel Corp.
- * (Written by Alexandru Gagniuc <alexandrux.gagniuc@intel.com> for Intel Corp.)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#ifndef _SOC_APOLLOLAKE_IOSF_H_
-#define _SOC_APOLLOLAKE_IOSF_H_
-
-#include <arch/io.h>
-
-#define IOSF_RTC_PORT_ID		0xD1
-#define  RTC_CONFIG			0x3400
-#define   RTC_CONFIG_UCMOS_ENABLE	(1 << 2)
-
-static inline void *iosf_address(uint16_t port, uint16_t reg)
-{
-	uintptr_t addr = (CONFIG_IOSF_BASE_ADDRESS | (port << 16) | (reg & ~3));
-	return (void *)addr;
-}
-
-static inline void iosf_write(uint16_t port, uint16_t reg, uint32_t val)
-{
-	write32(iosf_address(port, reg), val);
-}
-
-static inline uint32_t iosf_read(uint16_t port, uint16_t reg)
-{
-	return read32(iosf_address(port, reg));
-}
-#endif /* _SOC_APOLLOLAKE_IOSF_H_ */
diff --git a/src/soc/intel/apollolake/include/soc/pcr_ids.h b/src/soc/intel/apollolake/include/soc/pcr_ids.h
new file mode 100644
index 0000000000..b3e976e9fc
--- /dev/null
+++ b/src/soc/intel/apollolake/include/soc/pcr_ids.h
@@ -0,0 +1,30 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2017 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef SOC_INTEL_APL_PCR_H
+#define SOC_INTEL_APL_PCR_H
+
+/*
+ * Port ids.
+ */
+#define PID_GPIO_SW	0xC0
+#define PID_GPIO_S	0xC2
+#define PID_GPIO_NW	0xC4
+#define PID_GPIO_N	0xC5
+#define PID_GPIO_W	0xC7
+#define PID_ITSS	0xD0
+#define PID_RTC		0xD1
+
+#endif	/* SOC_INTEL_APL_PCR_H */