soc/intel/apollolake: Bring in delta for GLK SOC

Change-Id: I3e76726bb77f0277ab5776ae9d3d42b7eb389fe3
Signed-off-by: Hannah Williams <hannah.williams@intel.com>
Reviewed-on: https://review.coreboot.org/19603
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

1 files changed, 112 insertions, 0 deletions

diff --git a/src/soc/intel/apollolake/gpio_glk.c b/src/soc/intel/apollolake/gpio_glk.c
new file mode 100644
index 0000000000..fd73270d22
--- /dev/null
+++ b/src/soc/intel/apollolake/gpio_glk.c
@@ -0,0 +1,112 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015 Intel Corp.
+ * (Written by Alexandru Gagniuc <alexandrux.gagniuc@intel.com> for Intel Corp.)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <assert.h>
+#include <intelblocks/gpio.h>
+#include <intelblocks/pcr.h>
+#include <soc/pcr_ids.h>
+#include <soc/pm.h>
+
+static const struct reset_mapping rst_map[] = {
+	{ .logical = PAD_CFG0_LOGICAL_RESET_PWROK, .chipset = 0U << 30 },
+	{ .logical = PAD_CFG0_LOGICAL_RESET_DEEP, .chipset = 1U << 30 },
+	{ .logical = PAD_CFG0_LOGICAL_RESET_PLTRST, .chipset = 2U << 30 },
+};
+
+static const struct pad_community glk_gpio_communities[] = {
+	{
+		.port = PID_GPIO_NW,
+		.first_pad = NW_OFFSET,
+		.last_pad = GPIO_214,
+		.num_gpi_regs = NUM_NW_GPI_REGS,
+		.gpi_status_offset = 0,
+		.pad_cfg_base = PAD_CFG_BASE,
+		.host_own_reg_0 = HOSTSW_OWN_REG_0,
+		.gpi_smi_sts_reg_0 = GPI_SMI_STS_0,
+		.gpi_smi_en_reg_0 = GPI_SMI_EN_0,
+		.max_pads_per_group = GPIO_MAX_NUM_PER_GROUP,
+		.name = "GPIO_NORTHWEST",
+		.acpi_path = "\\_SB.GPO0",
+		.reset_map = rst_map,
+		.num_reset_vals = ARRAY_SIZE(rst_map),
+	}, {
+		.port = PID_GPIO_N,
+		.first_pad = N_OFFSET,
+		.last_pad = GPIO_155,
+		.num_gpi_regs = NUM_N_GPI_REGS,
+		.gpi_status_offset = NUM_NW_GPI_REGS,
+		.pad_cfg_base = PAD_CFG_BASE,
+		.host_own_reg_0 = HOSTSW_OWN_REG_0,
+		.gpi_smi_sts_reg_0 = GPI_SMI_STS_0,
+		.gpi_smi_en_reg_0 = GPI_SMI_EN_0,
+		.max_pads_per_group = GPIO_MAX_NUM_PER_GROUP,
+		.name = "GPIO_NORTH",
+		.acpi_path = "\\_SB.GPO1",
+		.reset_map = rst_map,
+		.num_reset_vals = ARRAY_SIZE(rst_map),
+	}, {
+		.port = PID_GPIO_AUDIO,
+		.first_pad = AUDIO_OFFSET,
+		.last_pad = GPIO_175,
+		.num_gpi_regs = NUM_AUDIO_GPI_REGS,
+		.gpi_status_offset = NUM_NW_GPI_REGS + NUM_N_GPI_REGS,
+		.pad_cfg_base = PAD_CFG_BASE,
+		.host_own_reg_0 = HOSTSW_OWN_REG_0,
+		.gpi_smi_sts_reg_0 = GPI_SMI_STS_0,
+		.gpi_smi_en_reg_0 = GPI_SMI_EN_0,
+		.max_pads_per_group = GPIO_MAX_NUM_PER_GROUP,
+		.name = "GPIO_AUDIO",
+		.acpi_path = "\\_SB.GPO2",
+		.reset_map = rst_map,
+		.num_reset_vals = ARRAY_SIZE(rst_map),
+	}, {
+		.port = PID_GPIO_SCC,
+		.first_pad = SCC_OFFSET,
+		.last_pad = GPIO_209,
+		.num_gpi_regs = NUM_SCC_GPI_REGS,
+		.gpi_status_offset = NUM_NW_GPI_REGS + NUM_N_GPI_REGS +
+			NUM_AUDIO_GPI_REGS,
+		.pad_cfg_base = PAD_CFG_BASE,
+		.host_own_reg_0 = HOSTSW_OWN_REG_0,
+		.gpi_smi_sts_reg_0 = GPI_SMI_STS_0,
+		.gpi_smi_en_reg_0 = GPI_SMI_EN_0,
+		.max_pads_per_group = GPIO_MAX_NUM_PER_GROUP,
+		.name = "GPIO_SCC",
+		.acpi_path = "\\_SB.GPO3",
+		.reset_map = rst_map,
+		.num_reset_vals = ARRAY_SIZE(rst_map),
+	},
+};
+
+const struct pad_community *soc_gpio_get_community(size_t *num_communities)
+{
+	*num_communities = ARRAY_SIZE(glk_gpio_communities);
+	return glk_gpio_communities;
+}
+
+const struct pmc_to_gpio_route *soc_pmc_gpio_routes(size_t *num)
+{
+	static const struct pmc_to_gpio_route routes[] = {
+		{ PMC_GPE_NW_31_0, GPIO_GPE_NW_31_0 },
+		{ PMC_GPE_NW_63_32, GPIO_GPE_NW_63_32 },
+		{ PMC_GPE_N_31_0, GPIO_GPE_N_31_0 },
+		{ PMC_GPE_N_63_32, GPIO_GPE_N_63_32 },
+		{ PMC_GPE_N_95_64, GPIO_GPE_N_95_64 },
+	};
+	*num = ARRAY_SIZE(routes);
+	return routes;
+}