diff options
| author | Bora Guvendik <bora.guvendik@intel.com> | 2017-11-22 13:48:12 -0800 |
|---|---|---|
| committer | Aaron Durbin <adurbin@chromium.org> | 2018-02-16 03:59:29 +0000 |
| commit | 3f672323b5f5cd6eaf955a31ebd0f73685f1d257 (patch) | |
| tree | c619cda6d614a0c37c873a8fe52d68f0439592eb /src/soc/intel/apollolake/gpio_apl.c | |
| parent | 7e2fe06a46ad3c44b1eb77651c27d4b9166033a6 (diff) | |
soc/intel/common/block/gpio: Change group offset calculation
Add group information for each gpio community and use it to
calculate offset of a pad within its group. Original implementation
assumed that the number of gpios in each group is same but that lead to
a bug for cnl since numbers differ for each group.
BUG=b:69616750
TEST=Need to test again on SKL,CNL,APL,GLK
Change-Id: I02ab1d878bc83d32222be074bd2db5e23adaf580
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/22571
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc/intel/apollolake/gpio_apl.c')
| -rw-r--r-- | src/soc/intel/apollolake/gpio_apl.c | 30 |
1 files changed, 30 insertions, 0 deletions
diff --git a/src/soc/intel/apollolake/gpio_apl.c b/src/soc/intel/apollolake/gpio_apl.c index a774470fc5..265e613d61 100644 --- a/src/soc/intel/apollolake/gpio_apl.c +++ b/src/soc/intel/apollolake/gpio_apl.c @@ -27,6 +27,28 @@ static const struct reset_mapping rst_map[] = { { .logical = PAD_CFG0_LOGICAL_RESET_PLTRST, .chipset = 2U << 30 }, }; +static const struct pad_group apl_community_n_groups[] = { + INTEL_GPP(N_OFFSET, N_OFFSET, GPIO_31), /* NORTH 0 */ + INTEL_GPP(N_OFFSET, GPIO_32, TRST_B), /* NORTH 1 */ + INTEL_GPP(N_OFFSET, TMS, SVID0_CLK), /* NORTH 2 */ +}; + +static const struct pad_group apl_community_w_groups[] = { + INTEL_GPP(W_OFFSET, W_OFFSET, OSC_CLK_OUT_1),/* WEST 0 */ + INTEL_GPP(W_OFFSET, OSC_CLK_OUT_2, SUSPWRDNACK),/* WEST 1 */ +}; + +static const struct pad_group apl_community_sw_groups[] = { + INTEL_GPP(SW_OFFSET, SW_OFFSET, SMB_ALERTB), /* SOUTHWEST 0 */ + INTEL_GPP(SW_OFFSET, SMB_CLK, LPC_FRAMEB), /* SOUTHWEST 1 */ +}; + +static const struct pad_group apl_community_nw_groups[] = { + INTEL_GPP(NW_OFFSET, NW_OFFSET, PROCHOT_B), /* NORTHWEST 0 */ + INTEL_GPP(NW_OFFSET, PMIC_I2C_SCL, GPIO_106),/* NORTHWEST 1 */ + INTEL_GPP(NW_OFFSET, GPIO_109, GPIO_123), /* NORTHWEST 2 */ +}; + static const struct pad_community apl_gpio_communities[] = { { .port = PID_GPIO_SW, @@ -43,6 +65,8 @@ static const struct pad_community apl_gpio_communities[] = { .acpi_path = "\\_SB.GPO3", .reset_map = rst_map, .num_reset_vals = ARRAY_SIZE(rst_map), + .groups = apl_community_sw_groups, + .num_groups = ARRAY_SIZE(apl_community_sw_groups), }, { .port = PID_GPIO_W, .first_pad = W_OFFSET, @@ -58,6 +82,8 @@ static const struct pad_community apl_gpio_communities[] = { .acpi_path = "\\_SB.GPO2", .reset_map = rst_map, .num_reset_vals = ARRAY_SIZE(rst_map), + .groups = apl_community_w_groups, + .num_groups = ARRAY_SIZE(apl_community_w_groups), }, { .port = PID_GPIO_NW, .first_pad = NW_OFFSET, @@ -73,6 +99,8 @@ static const struct pad_community apl_gpio_communities[] = { .acpi_path = "\\_SB.GPO1", .reset_map = rst_map, .num_reset_vals = ARRAY_SIZE(rst_map), + .groups = apl_community_nw_groups, + .num_groups = ARRAY_SIZE(apl_community_nw_groups), }, { .port = PID_GPIO_N, .first_pad = N_OFFSET, @@ -89,6 +117,8 @@ static const struct pad_community apl_gpio_communities[] = { .acpi_path = "\\_SB.GPO0", .reset_map = rst_map, .num_reset_vals = ARRAY_SIZE(rst_map), + .groups = apl_community_n_groups, + .num_groups = ARRAY_SIZE(apl_community_n_groups), } }; |