diff options
| author | Michael Niewöhner <foss@mniewoehner.de> | 2019-10-22 23:05:06 +0200 |
|---|---|---|
| committer | Nico Huber <nico.h@gmx.de> | 2019-11-04 19:25:02 +0000 |
| commit | 7736bfc443a913a9cde46406bcfc38015ec71f47 (patch) | |
| tree | 5b107551301bbaadc538b0c2ac7c52125462beb3 /src/soc/intel/apollolake/cpu.c | |
| parent | e75a64f822931a5fbdd80f20c4d168a5c346e01a (diff) | |
soc/intel/sgx: convert SGX and PRMRR devicetree options to Kconfig
The devicetree is not made for user-choosable options, thus introduce
Kconfig options for both SGX and the corresponding PRMRR size.
The PRMRR size Kconfig has been implemented as a maximum value. At
runtime the final PRMRR size gets selected by checking the supported
values in MSR_PRMRR_VALID_CONFIG and trying to select the value nearest
to the chosen one.
When "Maximum" is chosen, the highest possibly value from the MSR gets
used. When a too strict limit is set, coreboot will die, printing an
error message.
Tested successfully on X11SSM-F
Change-Id: I5f08e85898304bba6680075ca5d6bce26aef9a4d
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35799
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'src/soc/intel/apollolake/cpu.c')
| -rw-r--r-- | src/soc/intel/apollolake/cpu.c | 11 |
1 files changed, 3 insertions, 8 deletions
diff --git a/src/soc/intel/apollolake/cpu.c b/src/soc/intel/apollolake/cpu.c index 6e826b863c..0b9466c4c5 100644 --- a/src/soc/intel/apollolake/cpu.c +++ b/src/soc/intel/apollolake/cpu.c @@ -72,13 +72,10 @@ static const struct reg_script core_msr_script[] = { void soc_core_init(struct device *cpu) { - config_t *conf = config_of_soc(); - /* Clear out pending MCEs */ /* TODO(adurbin): Some of these banks are core vs package scope. For now every CPU clears every bank. */ - if ((CONFIG(SOC_INTEL_COMMON_BLOCK_SGX) && conf->sgx_enable) || - acpi_get_sleep_type() == ACPI_S5) + if (CONFIG(SOC_INTEL_COMMON_BLOCK_SGX_ENABLE) || acpi_get_sleep_type() == ACPI_S5) mca_configure(); /* Set core MSRs */ @@ -91,7 +88,7 @@ void soc_core_init(struct device *cpu) enable_pm_timer_emulation(); /* Configure Core PRMRR for SGX. */ - if (CONFIG(SOC_INTEL_COMMON_BLOCK_SGX) && conf->sgx_enable) + if (CONFIG(SOC_INTEL_COMMON_BLOCK_SGX_ENABLE)) prmrr_core_configure(); /* Set Max Non-Turbo ratio if RAPL is disabled. */ @@ -255,11 +252,9 @@ static void relocation_handler(int cpu, uintptr_t curr_smbase, static void post_mp_init(void) { - config_t *conf = config_of_soc(); - smm_southbridge_enable(PWRBTN_EN | GBL_EN); - if (CONFIG(SOC_INTEL_COMMON_BLOCK_SGX) && conf->sgx_enable) + if (CONFIG(SOC_INTEL_COMMON_BLOCK_SGX_ENABLE)) mp_run_on_all_cpus(sgx_configure, NULL); } |