diff options
| author | Mario Scheithauer <mario.scheithauer@siemens.com> | 2019-03-07 09:48:33 +0100 |
|---|---|---|
| committer | Nico Huber <nico.h@gmx.de> | 2019-03-08 14:14:41 +0000 |
| commit | e4cb23c68225d2973f771d61b5dc7725a1c92c2f (patch) | |
| tree | 51a8f8ad7c89f65d1b451a9e0815333665d47707 /src/soc/intel/apollolake/cpu.c | |
| parent | be11236a4d9934c93ee284167e86386db3205d35 (diff) | |
src/soc/intel/apollolake/cpu.c: Set up local APIC
Some Apollo Lake mainboards use SeaBIOS as payload. SeaBIOS requires the
initialization of the programmable interrupt controller (PIC) for
faultless operation. The PIC mode is need for USB support (e.g.
keyboard, memory stick) and for some Option ROMs (e.g. PXE ROM).
Therefore add setup_lapic() to configure the APIC.
Change-Id: I00b339ce1850729023db74da7f8845927a95dcc6
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31802
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/apollolake/cpu.c')
| -rw-r--r-- | src/soc/intel/apollolake/cpu.c | 6 |
1 files changed, 5 insertions, 1 deletions
diff --git a/src/soc/intel/apollolake/cpu.c b/src/soc/intel/apollolake/cpu.c index 741e08c9b7..8f1d933a0b 100644 --- a/src/soc/intel/apollolake/cpu.c +++ b/src/soc/intel/apollolake/cpu.c @@ -2,7 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2015-2017 Intel Corp. - * Copyright (C) 2017 Siemens AG, Inc. + * Copyright (C) 2017-2019 Siemens AG * (Written by Andrey Petrov <andrey.petrov@intel.com> for Intel Corp.) * (Written by Alexandru Gagniuc <alexandrux.gagniuc@intel.com> for Intel Corp.) * @@ -23,6 +23,7 @@ #include "chip.h" #include <cpu/cpu.h> #include <cpu/x86/cache.h> +#include <cpu/x86/lapic.h> #include <cpu/x86/mp.h> #include <cpu/intel/microcode.h> #include <cpu/intel/turbo.h> @@ -161,6 +162,9 @@ static void pre_mp_init(void) } x86_setup_mtrrs_with_detect(); x86_mtrr_check(); + + /* Enable the local CPU apics */ + setup_lapic(); } #if !CONFIG(SOC_INTEL_COMMON_BLOCK_CPU_MPINIT) |