diff options
| author | Ravi Sarawadi <ravishankar.sarawadi@intel.com> | 2016-09-09 14:08:50 -0700 |
|---|---|---|
| committer | Aaron Durbin <adurbin@chromium.org> | 2016-10-16 02:52:48 +0200 |
| commit | a52f883b100f3229dd4d86c81c08781993861f73 (patch) | |
| tree | 349aea8ff41aff195dba41561369dd4d6ccea35a /src/soc/intel/apollolake/cpu.c | |
| parent | 63583f09872e26edb80fd891547d128abe4c6df9 (diff) | |
soc/apollolake: Add soc core init
Skip FSP initiated core/MP init as it is implemented and initiated
in coreboot.
Add soc core init to set up the following feature MSRs:
1. C-states
2. IO/Mwait redirection
BUG=chrome-os-partner:56922
BRANCH=None
TEST= Check C-state functioning using 'powertop'. Check 0xE2 and
0xE4 MSR to verify IO/Mwait redirection.
Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com>
Change-Id: I97c3d82f654be30a0d2d88cb68c8212af3d6f767
Reviewed-on: https://review.coreboot.org/16587
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc/intel/apollolake/cpu.c')
| -rw-r--r-- | src/soc/intel/apollolake/cpu.c | 23 |
1 files changed, 22 insertions, 1 deletions
diff --git a/src/soc/intel/apollolake/cpu.c b/src/soc/intel/apollolake/cpu.c index e67842c369..bd5cff50a9 100644 --- a/src/soc/intel/apollolake/cpu.c +++ b/src/soc/intel/apollolake/cpu.c @@ -25,11 +25,32 @@ #include <cpu/x86/mtrr.h> #include <device/device.h> #include <device/pci.h> +#include <reg_script.h> #include <soc/cpu.h> +#include <soc/iomap.h> #include <soc/smm.h> +static const struct reg_script core_msr_script[] = { + /* Enable C-state and IO/MWAIT redirect */ + REG_MSR_WRITE(MSR_PMG_CST_CONFIG_CONTROL, + (PKG_C_STATE_LIMIT_C2_MASK | CORE_C_STATE_LIMIT_C10_MASK + | IO_MWAIT_REDIRECT_MASK | CST_CFG_LOCK_MASK)), + /* Power Management I/O base address for I/O trapping to C-states */ + REG_MSR_WRITE(MSR_PMG_IO_CAPTURE_BASE, + (ACPI_PMIO_CST_REG | (PMG_IO_BASE_CST_RNG_BLK_SIZE << 16))), + /* Disable C1E */ + REG_MSR_RMW(MSR_POWER_CTL, ~0x2, 0), + REG_SCRIPT_END +}; + +static void soc_core_init(device_t cpu) +{ + /* Set core MSRs */ + reg_script_run(core_msr_script); +} + static struct device_operations cpu_dev_ops = { - .init = DEVICE_NOOP, + .init = soc_core_init, }; static struct cpu_device_id cpu_table[] = { |