diff options
| author | Subrata Banik <subrata.banik@intel.com> | 2018-05-09 14:55:09 +0530 |
|---|---|---|
| committer | Subrata Banik <subrata.banik@intel.com> | 2018-06-06 06:23:45 +0000 |
| commit | c4986eb7f4eee0f305c6a6f05b45effae152062c (patch) | |
| tree | 46185566d98e49bbfa60acfdedc60e1e423823d3 /src/soc/intel/apollolake/chip.h | |
| parent | f513cebd8b966c15e3c8abcd2d0f540607ea5964 (diff) | |
soc/intel/common/block: Add common chip config block
Adding common chip config structure which will be used to return data to
common code. When common code requires soc data, code used to fetch
entire soc config structure. With this change, common code will only get
the data/structure which is required by common code and not entire
config.
For now, adding i2c, gspi and lockdown configuration which will be used
by common code.
BUG=none
BRANCH=b:78109109
TEST=compile code for APL/SKL/CNL. Boot using SKL/APL/CNL and check
values are returned properly using common structure.
Change-Id: I7f1671e064782397d3ace066a08bf1333192b21a
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/26189
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Hannah Williams <hannah.williams@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/apollolake/chip.h')
| -rw-r--r-- | src/soc/intel/apollolake/chip.h | 10 |
1 files changed, 4 insertions, 6 deletions
diff --git a/src/soc/intel/apollolake/chip.h b/src/soc/intel/apollolake/chip.h index af465df111..4f586acfd1 100644 --- a/src/soc/intel/apollolake/chip.h +++ b/src/soc/intel/apollolake/chip.h @@ -20,6 +20,7 @@ #define _SOC_APOLLOLAKE_CHIP_H_ #include <commonlib/helpers.h> +#include <intelblocks/chip.h> #include <intelblocks/gspi.h> #include <soc/gpe.h> #include <soc/gpio.h> @@ -31,7 +32,6 @@ #define MAX_PCIE_PORTS 6 #define CLKREQ_DISABLED 0xf -#define APOLLOLAKE_I2C_DEV_MAX 8 enum pnp_settings { PNP_PERF, @@ -40,8 +40,9 @@ enum pnp_settings { }; struct soc_intel_apollolake_config { - /* GSPI */ - struct gspi_cfg gspi[CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX]; + + /* Common structure containing soc config data required by common code*/ + struct soc_intel_common_config common_soc_config; /* * Mapping from PCIe root port to CLKREQ input on the SOC. The SOC has @@ -98,9 +99,6 @@ struct soc_intel_apollolake_config { /* Configure serial IRQ (SERIRQ) line. */ enum serirq_mode serirq_mode; - /* I2C bus configuration */ - struct dw_i2c_bus_config i2c[APOLLOLAKE_I2C_DEV_MAX]; - uint8_t gpe0_dw1; /* GPE0_63_32 STS/EN */ uint8_t gpe0_dw2; /* GPE0_95_64 STS/EN */ uint8_t gpe0_dw3; /* GPE0_127_96 STS/EN */ |