diff options
| author | Michael Niewöhner <foss@mniewoehner.de> | 2019-10-22 23:05:06 +0200 |
|---|---|---|
| committer | Nico Huber <nico.h@gmx.de> | 2019-11-04 19:25:02 +0000 |
| commit | 7736bfc443a913a9cde46406bcfc38015ec71f47 (patch) | |
| tree | 5b107551301bbaadc538b0c2ac7c52125462beb3 /src/soc/intel/apollolake/chip.h | |
| parent | e75a64f822931a5fbdd80f20c4d168a5c346e01a (diff) | |
soc/intel/sgx: convert SGX and PRMRR devicetree options to Kconfig
The devicetree is not made for user-choosable options, thus introduce
Kconfig options for both SGX and the corresponding PRMRR size.
The PRMRR size Kconfig has been implemented as a maximum value. At
runtime the final PRMRR size gets selected by checking the supported
values in MSR_PRMRR_VALID_CONFIG and trying to select the value nearest
to the chosen one.
When "Maximum" is chosen, the highest possibly value from the MSR gets
used. When a too strict limit is set, coreboot will die, printing an
error message.
Tested successfully on X11SSM-F
Change-Id: I5f08e85898304bba6680075ca5d6bce26aef9a4d
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35799
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'src/soc/intel/apollolake/chip.h')
| -rw-r--r-- | src/soc/intel/apollolake/chip.h | 12 |
1 files changed, 0 insertions, 12 deletions
diff --git a/src/soc/intel/apollolake/chip.h b/src/soc/intel/apollolake/chip.h index 85cfff9af5..e5045d01b1 100644 --- a/src/soc/intel/apollolake/chip.h +++ b/src/soc/intel/apollolake/chip.h @@ -139,18 +139,6 @@ struct soc_intel_apollolake_config { /* GPIO SD card detect pin */ unsigned int sdcard_cd_gpio; - /* PRMRR size setting with three options - * 0x02000000 - 32MiB - * 0x04000000 - 64MiB - * 0x08000000 - 128MiB */ - uint32_t PrmrrSize; - - /* Enable SGX feature. - * Enabling SGX feature is 2 step process, - * (1) set sgx_enable = 1 - * (2) set PrmrrSize to supported size */ - uint8_t sgx_enable; - /* Select PNP Settings. * (0) Performance, * (1) Power |