diff options
| author | Shaunak Saha <shaunak.saha@intel.com> | 2016-06-07 02:06:28 -0700 |
|---|---|---|
| committer | Aaron Durbin <adurbin@chromium.org> | 2016-07-02 03:30:28 +0200 |
| commit | 5b6c5a500ed416f033a22eed1d8174063ebaf143 (patch) | |
| tree | 6dca69cee7e72887a48579c25f58141713dfc58a /src/soc/intel/apollolake/chip.h | |
| parent | 0b806285a7819397a5fede24cfdcf7c09d0caa1c (diff) | |
soc/intel/apollolake: Add GPE routing code
This patch adds the basic framework for SCI to GPE routing code.
BUG = chrome-os-partner:53438
TEST = Toogle pch_sci_l from ec console using gpioset command and
see that the sci counter increases in /sys/firmware/acpi/interrupt
and also 9 in /proc/interrupts.
Change-Id: I3b3198276530bf6513d94e9bea02ab9751212adf
Signed-off-by: Shaunak Saha <shaunak.saha@intel.com>
Reviewed-on: https://review.coreboot.org/15324
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
Diffstat (limited to 'src/soc/intel/apollolake/chip.h')
| -rw-r--r-- | src/soc/intel/apollolake/chip.h | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/src/soc/intel/apollolake/chip.h b/src/soc/intel/apollolake/chip.h index c83f9739fd..aabd42df42 100644 --- a/src/soc/intel/apollolake/chip.h +++ b/src/soc/intel/apollolake/chip.h @@ -21,6 +21,7 @@ #include <soc/gpio.h> #include <soc/intel/common/lpss_i2c.h> #include <device/i2c.h> +#include <soc/pm.h> #define CLKREQ_DISABLED 0xf #define APOLLOLAKE_I2C_DEV_MAX 8 @@ -96,6 +97,10 @@ struct soc_intel_apollolake_config { /* I2C bus configuration */ struct apollolake_i2c_config i2c[APOLLOLAKE_I2C_DEV_MAX]; + + uint8_t gpe0_dw1; /* GPE0_63_32 STS/EN */ + uint8_t gpe0_dw2; /* GPE0_95_64 STS/EN */ + uint8_t gpe0_dw3; /* GPE0_127_96 STS/EN */ }; #endif /* _SOC_APOLLOLAKE_CHIP_H_ */ |