diff options
| author | Alexandru Gagniuc <alexandrux.gagniuc@intel.com> | 2016-04-04 10:47:49 -0700 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2016-05-06 18:58:31 +0200 |
| commit | 3aa34a8167c0e0f0ecdb823b5ab1de5c3b171f06 (patch) | |
| tree | 5dadf6805475858b8c642599a1fd25eb39c9cae8 /src/soc/intel/apollolake/chip.h | |
| parent | 665fca156c2c22884b5b796e3f365f5d5ed61733 (diff) | |
soc/apollolake/lpc: Allow configuring SERIRQ via devicetree
Every other SOC uses a CONFIG_* flag to enable or disable SERIRQ
continuous mode. Why they do that is beyond me, but the way we
implement it on apollolake is via devicetree.
Change-Id: I6e05758e5e264c6b0015467dd25add3bffe2b040
Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc@intel.com>
Reviewed-on: https://review.coreboot.org/14586
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc/intel/apollolake/chip.h')
| -rw-r--r-- | src/soc/intel/apollolake/chip.h | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/src/soc/intel/apollolake/chip.h b/src/soc/intel/apollolake/chip.h index 9d2bc46d61..d74084ebff 100644 --- a/src/soc/intel/apollolake/chip.h +++ b/src/soc/intel/apollolake/chip.h @@ -20,6 +20,13 @@ #define CLKREQ_DISABLED 0xf +/* Serial IRQ control. SERIRQ_QUIET is the default (0). */ +enum serirq_mode { + SERIRQ_QUIET, + SERIRQ_CONTINUOUS, + SERIRQ_OFF, +}; + struct soc_intel_apollolake_config { /* * Mapping from PCIe root port to CLKREQ input on the SOC. The SOC has @@ -32,6 +39,9 @@ struct soc_intel_apollolake_config { uint8_t pcie_rp3_clkreq_pin; uint8_t pcie_rp4_clkreq_pin; uint8_t pcie_rp5_clkreq_pin; + + /* Configure serial IRQ (SERIRQ) line. */ + enum serirq_mode serirq_mode; }; #endif /* _SOC_APOLLOLAKE_CHIP_H_ */ |