soc/intel/apollolake: Add PNP config

1. Programs PNP values for AUNIT, BUNIT & TUNIT registers
as per reference code.
2. A new configuration option pnp_settings is introduced in
devicetree.cb to select PNP settings among performance,
power, power & performance.

TEST = built and booted glkrvp, verfied that the callback gets
control, verified warm and cold reboots.

Change-Id: Ibd70a42c9406941c8a93cc972f22c2475e9d0200
Signed-off-by: Divya Chellap <divya.chellappa@intel.com>
Reviewed-on: https://review.coreboot.org/22488
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

1 files changed, 12 insertions, 0 deletions

diff --git a/src/soc/intel/apollolake/chip.h b/src/soc/intel/apollolake/chip.h
index eaa932a7de..92e814b622 100644
--- a/src/soc/intel/apollolake/chip.h
+++ b/src/soc/intel/apollolake/chip.h
@@ -30,6 +30,12 @@
 #define CLKREQ_DISABLED		0xf
 #define APOLLOLAKE_I2C_DEV_MAX	8
 
+enum pnp_settings {
+	PNP_PERF,
+	PNP_POWER,
+	PNP_PERF_POWER,
+};
+
 struct soc_intel_apollolake_config {
 	/*
 	 * Mapping from PCIe root port to CLKREQ input on the SOC. The SOC has
@@ -133,6 +139,12 @@ struct soc_intel_apollolake_config {
 	 * (1) set sgx_enable = 1
 	 * (2) set PrmrrSize to supported size */
 	uint8_t sgx_enable;
+
+	/* Select PNP Settings.
+	 * (0) Performance,
+	 * (1) Power
+	 * (2) Power & Performance */
+	enum pnp_settings pnp_settings;
 };
 
 typedef struct soc_intel_apollolake_config config_t;