diff options
| author | Joey Peng <joey.peng@lcfc.corp-partner.google.com> | 2023-04-25 15:18:00 +0800 |
|---|---|---|
| committer | Nick Vaccaro <nvaccaro@google.com> | 2023-05-02 19:03:38 +0000 |
| commit | ea2a38be323173075db3b13729a4006ea1fef72d (patch) | |
| tree | aa0a75277ab3004a626c8a8b215ef9b21abad192 /src/soc/intel/apollolake/chip.c | |
| parent | 9718e2616a2874c132da1b7c41c77b3dfec52eac (diff) | |
soc/intel/alderlake: Disable C1E on RPL CPUs
Since disabling C1E could improve acoustic noise for RPL, add judgement
in SOC code to disable C1E on RPL CPUs and enabling it on ADL CPUs .
BUG=b:278654939
TEST:emerge-brya coreboot
Signed-off-by: Joey Peng <joey.peng@lcfc.corp-partner.google.com>
Change-Id: Ic2d2d5d6075de25141c1d08ec18838731c63a342
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74727
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Diffstat (limited to 'src/soc/intel/apollolake/chip.c')
0 files changed, 0 insertions, 0 deletions