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authorAaron Durbin <adurbin@chromium.org>2016-07-01 16:36:03 -0500
committerAaron Durbin <adurbin@chromium.org>2016-07-02 03:22:32 +0200
commitfadfc2e2f6abbcaea7bbc92c13716c5382443993 (patch)
treed4c5ba325a8aa0a33c1fe17fd8be8d854d726d41 /src/soc/intel/apollolake/chip.c
parent4025e26fc585d372a39087c67b6efd4b410a89bd (diff)
soc/intel/apollolake: handle p2sb quirks
The P2SB device is device 0xd and function 0. If hidden that causes the latter pci devices on function >= 1 to not be probed in the kernel. This is also a problem for coreboot if the P2SB device is hidden by FSP. That means the coreboot driver won't be ran. Therefore, provide hide and unhide functions for the P2SB device. The other quirk is to allow the GPIO devices to work correctly. Those devices are ACPI devices. However, their resources are sub-regions within the P2SB BAR. Sadly, linux doesn't handle ACPI devices being children of PCI devices. This leads to resource conflict errors when the P2SB device is visible. For the time being keep the P2SB device hidden, but also ensure the resources it is using are accounted for and reserved. The fallout of that is the PMC and SPI device are no longer probed by the kernel. BUG=chrome-os-partner:53017 TEST=Ensured P2SB device is visible and pci resources are allocated correctly for the devices. Change-Id: I24e59bbde74310e1ce8425b344a3ad0b88702153 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/15530 Tested-by: build bot (Jenkins) Reviewed-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/soc/intel/apollolake/chip.c')
-rw-r--r--src/soc/intel/apollolake/chip.c14
1 files changed, 13 insertions, 1 deletions
diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c
index 68459e602a..00470a201a 100644
--- a/src/soc/intel/apollolake/chip.c
+++ b/src/soc/intel/apollolake/chip.c
@@ -33,6 +33,7 @@
#include <soc/pci_devs.h>
#include <spi-generic.h>
#include <soc/pm.h>
+#include <soc/p2sb.h>
#include "chip.h"
@@ -153,6 +154,14 @@ static void soc_init(void *data)
range_entry_init(&range, 0x200000, 4ULL*GiB, 0);
fsp_silicon_init(&range);
+ /*
+ * Keep the P2SB device visible so it and the other devices are
+ * visible in coreboot for driver support and PCI resource allocation.
+ * There is a UPD setting for this, but it's more consistent to use
+ * hide and unhide symmetrically.
+ */
+ p2sb_unhide();
+
/* Allocate ACPI NVS in CBMEM */
gnvs = cbmem_add(CBMEM_ID_ACPI_GNVS, sizeof(*gnvs));
}
@@ -346,8 +355,11 @@ static void fsp_notify_dummy(void *arg)
fsp_handle_reset(ret);
}
/* Call END_OF_FIRMWARE Notify after READY_TO_BOOT Notify */
- if (ph == READY_TO_BOOT)
+ if (ph == READY_TO_BOOT) {
fsp_notify_dummy((void *)END_OF_FIRMWARE);
+ /* Hide the P2SB device to align with previous behavior. */
+ p2sb_hide();
+ }
}
BOOT_STATE_INIT_ENTRY(BS_DEV_RESOURCES, BS_ON_EXIT, fsp_notify_dummy,