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authorSeunghwan Kim <sh_.kim@samsung.com>2019-01-24 16:17:44 +0900
committerPatrick Georgi <pgeorgi@google.com>2019-01-29 12:31:03 +0000
commitf7fd9b145e52d83fa2da16644e11538da17bd430 (patch)
treee9f924ee593838d8c550547fa9af40ce82e553df /src/soc/intel/apollolake/chip.c
parent1e504f7811273b5a6a94bb82b94031112069dd56 (diff)
soc/intel/apollolake: Add GLK usb2eye configuration override
Now we have usb2eye configuration register in FSPUPD, so we need to add an interface to override usb2eye setting. BRANCH=octopus BUG=NONE TEST=Verified usb2eye custom setting works Change-Id: I5c500964658072eaaf59364242aa928df25d99d1 Signed-off-by: Seunghwan Kim <sh_.kim@samsung.com> Reviewed-on: https://review.coreboot.org/c/31060 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Diffstat (limited to 'src/soc/intel/apollolake/chip.c')
-rw-r--r--src/soc/intel/apollolake/chip.c16
1 files changed, 16 insertions, 0 deletions
diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c
index afbb45cd04..a3ce48383d 100644
--- a/src/soc/intel/apollolake/chip.c
+++ b/src/soc/intel/apollolake/chip.c
@@ -593,6 +593,22 @@ static void glk_fsp_silicon_init_params_cb(
struct soc_intel_apollolake_config *cfg, FSP_S_CONFIG *silconfig)
{
#if IS_ENABLED(CONFIG_SOC_INTEL_GLK)
+ uint8_t port;
+
+ for (port = 0; port < APOLLOLAKE_USB2_PORT_MAX; port++) {
+ if (!cfg->usb2eye[port].Usb20OverrideEn)
+ continue;
+
+ silconfig->Usb2AfePehalfbit[port] =
+ cfg->usb2eye[port].Usb20PerPortTxPeHalf;
+ silconfig->Usb2AfePetxiset[port] =
+ cfg->usb2eye[port].Usb20PerPortPeTxiSet;
+ silconfig->Usb2AfeTxiset[port] =
+ cfg->usb2eye[port].Usb20PerPortTxiSet;
+ silconfig->Usb2AfePredeemp[port] =
+ cfg->usb2eye[port].Usb20IUsbTxEmphasisEn;
+ }
+
silconfig->Gmm = 0;
/* On Geminilake, we need to override the default FSP PCIe de-emphasis