diff options
| author | John Zhao <john.zhao@intel.com> | 2019-01-28 16:04:35 -0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-01-30 13:27:30 +0000 |
| commit | 9a4beb429d87f9c0f46b7f945432a955cd88c962 (patch) | |
| tree | 065966fa1d457b3ca976a29206dc1046bf265c25 /src/soc/intel/apollolake/chip.c | |
| parent | a35904b29cf4f2ae9ab56122a3b0ee6aa6ffb823 (diff) | |
soc/intel/apollolake: Sync fsp upd structure update
FSP 2.0.9 provides UPD interface to adjust integrated filter
value, usb3 LDO and pmic vdd2 voltage. Change coreboot upd
structure to sync with fsp 2.0.9 release.
BUG=b:123398358
CQ-DEPEND=CL:*817128
TEST=Verified yorp boots to kernel.
Change-Id: I3d17dfbe58bdc5222378459723da8e9ac0573510
Signed-off-by: John Zhao <john.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/c/31131
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/soc/intel/apollolake/chip.c')
| -rw-r--r-- | src/soc/intel/apollolake/chip.c | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c index a3ce48383d..cddfe4436f 100644 --- a/src/soc/intel/apollolake/chip.c +++ b/src/soc/intel/apollolake/chip.c @@ -639,6 +639,21 @@ static void glk_fsp_silicon_init_params_cb( * Options to disable XHCI Link Compliance Mode. */ silconfig->DisableComplianceMode = cfg->DisableComplianceMode; + + /* + * Options to change USB3 ModPhy setting for Integrated Filter value. + */ + silconfig->ModPhyIfValue = cfg->ModPhyIfValue; + + /* + * Options to bump USB3 LDO voltage with 40mv. + */ + silconfig->ModPhyVoltageBump = cfg->ModPhyVoltageBump; + + /* + * Options to adjust PMIC Vdd2 voltage. + */ + silconfig->PmicVdd2Voltage = cfg->PmicVdd2Voltage; #endif } |