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authorJohn Zhao <john.zhao@intel.com>2019-01-10 12:13:38 -0800
committerPatrick Georgi <pgeorgi@google.com>2019-01-14 11:58:38 +0000
commit91600a318210e703704790afe28c073f5ecfab86 (patch)
tree636b84f37b6eda75e306a217dea0e79fe6561db5 /src/soc/intel/apollolake/chip.c
parente49b2f088f64b4a746491791c8e3727781a4ebb3 (diff)
soc/intel/apollolake: Add option to disable xHCI Link Compliance Mode
Provide options to disable xHCI Link Compliance Mode. Default is FALSE to not disable Compliance Mode. Set TRUE to disable Compliance Mode. BRANCH=octopus BUG=b:115699781 TEST=Verified booting to kernel. Change-Id: I2a486bc4c1a8578cfd7ac3d17103e889eaa25fe4 Signed-off-by: John Zhao <john.zhao@intel.com> Reviewed-on: https://review.coreboot.org/c/30816 Reviewed-by: Justin TerAvest <teravest@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/apollolake/chip.c')
-rw-r--r--src/soc/intel/apollolake/chip.c7
1 files changed, 6 insertions, 1 deletions
diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c
index 1c8f321924..b38265fdd4 100644
--- a/src/soc/intel/apollolake/chip.c
+++ b/src/soc/intel/apollolake/chip.c
@@ -571,8 +571,13 @@ static void glk_fsp_silicon_init_params_cb(
* FSP provides UPD interface to execute IPC command. In order to
* improve boot performance, configure PmicPmcIpcCtrl for PMC to program
* PMIC PCH_PWROK delay.
- */
+ */
silconfig->PmicPmcIpcCtrl = cfg->PmicPmcIpcCtrl;
+
+ /*
+ * Options to disable XHCI Link Compliance Mode.
+ */
+ silconfig->DisableComplianceMode = cfg->DisableComplianceMode;
#endif
}