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authorTim Wawrzynczak <twawrzynczak@chromium.org>2020-05-27 10:22:45 -0600
committerTim Wawrzynczak <twawrzynczak@chromium.org>2020-06-03 01:30:59 +0000
commit7c34865c9217c9d02dbfc2b5f7f939ef4d587728 (patch)
treeb10c26048c9e1dd2e41dfd7e18f476b2a0015ea8 /src/soc/intel/apollolake/chip.c
parentbebb2a1705b697fccf91a0f2c3a9d5870a27e9fa (diff)
soc/intel/apollolake: Reinstate APL_SKIP_SET_POWER_LIMITS
The config option APL_SKIP_SET_POWER_LIMITS was accidentally left out during the set_power_limits refactor (SHA 2adb50d32e8). This patch reinstates the config option which will cause APL boards to not set any power limits. TEST=util/abuild/abuild -p none -t siemens/mc_apl1 -a Change-Id: Iec9f9f340d50a1212b6ef20c2c0e1b66385ae1b2 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41786 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Diffstat (limited to 'src/soc/intel/apollolake/chip.c')
-rw-r--r--src/soc/intel/apollolake/chip.c12
1 files changed, 8 insertions, 4 deletions
diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c
index cc190bae24..f9af4f49d9 100644
--- a/src/soc/intel/apollolake/chip.c
+++ b/src/soc/intel/apollolake/chip.c
@@ -322,10 +322,14 @@ static void soc_init(void *data)
/* Allocate ACPI NVS in CBMEM */
cbmem_add(CBMEM_ID_ACPI_GNVS, sizeof(struct global_nvs_t));
- config = config_of_soc();
- /* Set RAPL MSR for Package power limits */
- soc_config = &config->power_limits_config;
- set_power_limits(MOBILE_SKU_PL1_TIME_SEC, soc_config);
+ if (CONFIG(APL_SKIP_SET_POWER_LIMITS)) {
+ printk(BIOS_INFO, "Skip setting RAPL per configuration\n");
+ } else {
+ config = config_of_soc();
+ /* Set RAPL MSR for Package power limits */
+ soc_config = &config->power_limits_config;
+ set_power_limits(MOBILE_SKU_PL1_TIME_SEC, soc_config);
+ }
/*
* FSP-S routes SCI to IRQ 9. With the help of this function you can