diff options
| author | Werner Zeh <werner.zeh@siemens.com> | 2019-02-01 12:32:51 +0100 |
|---|---|---|
| committer | Werner Zeh <werner.zeh@siemens.com> | 2019-02-05 06:34:44 +0000 |
| commit | 279afdc24b3c65275cad222be53b908bb0f752ef (patch) | |
| tree | c3f29ee274a0e6b70f7edfbbcadbd1bcea947d3b /src/soc/intel/apollolake/chip.c | |
| parent | 8a64b6fbdbbf32dafe84ff8d8c74a3a79f1ae169 (diff) | |
intel/apollolake: Add parameter to enable VTD in devicetree
The FSP has a parameter to enable or disable the VTD feature
(Intel's Virtualization Technology for Directed I/O). In current header
files for FSP-S (Apollo Lake and Gemini Lake) this parameter is set to
disabled per default. Therefore, if the FSP was not modified via BCT,
this feature is most likely disabled on all mainboards.
Add a chip parameter so that VTD can be enabled on mainboard level in
devicetree and therefore this feature can be activated if needed.
Change-Id: Ic0bfcf1719e1ccc678a932bf3d38c6dbce3556bc
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/31194
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/apollolake/chip.c')
| -rw-r--r-- | src/soc/intel/apollolake/chip.c | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c index de33e8217b..363450911a 100644 --- a/src/soc/intel/apollolake/chip.c +++ b/src/soc/intel/apollolake/chip.c @@ -754,6 +754,9 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *silupd) if (!xdci_can_enable()) dev->enabled = 0; silconfig->UsbOtg = dev->enabled; + + /* Set VTD feature according to devicetree */ + silconfig->VtdEnable = cfg->enable_vtd; } struct chip_operations soc_intel_apollolake_ops = { |