diff options
| author | Subrata Banik <subrata.banik@intel.com> | 2017-05-19 18:38:24 +0530 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2017-06-09 17:06:59 +0200 |
| commit | 208587e0f688988eb20ec89d2422d27f0fe7ad27 (patch) | |
| tree | 3aa4e4483418f9d7f077c7e772bd119f3be073e7 /src/soc/intel/apollolake/chip.c | |
| parent | 46a71782678b17aec49e938ab941a2604a5b9afe (diff) | |
soc/intel/apollolake: Use common systemagent code
This patch perform resource mapping for PCI,
fixed MMIO, DRAM and IMR's based on inputs given by SoC.
TEST=Ensure PCI root bridge 0:0:0 memory resource allocation
remains same between previous implementation and current
implementation.
Change-Id: I15a3b2fc46ec9063b54379d41996b9a1d612cfd2
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/19795
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc/intel/apollolake/chip.c')
| -rw-r--r-- | src/soc/intel/apollolake/chip.c | 9 |
1 files changed, 2 insertions, 7 deletions
diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c index 91bae2d3a2..ef63d2055b 100644 --- a/src/soc/intel/apollolake/chip.c +++ b/src/soc/intel/apollolake/chip.c @@ -219,7 +219,6 @@ static void set_power_limits(void) uint32_t power_unit; uint32_t tdp, min_power, max_power; uint32_t pl2_val; - uint32_t *rapl_mmio_reg; if (!dev || !dev->chip_info) { printk(BIOS_ERR, "BUG! Could not find SOC devicetree config\n"); @@ -272,15 +271,11 @@ static void set_power_limits(void) printk(BIOS_INFO, "RAPL PL2 %d.%dW\n", pl2_val / power_unit, 100 * (pl2_val % power_unit) / power_unit); - /* Get the MMIO address */ - rapl_mmio_reg = (void *)(uintptr_t) (MCH_BASE_ADDRESS + - MCHBAR_RAPL_PPL); - /* Setting RAPL MMIO register for Power limits. * RAPL driver is using MSR instead of MMIO. * So, disabled LIMIT_EN bit for MMIO. */ - write32(rapl_mmio_reg, limit.lo & ~(PKG_POWER_LIMIT_EN)); - write32(rapl_mmio_reg + 1, limit.hi & ~(PKG_POWER_LIMIT_EN)); + MCHBAR32(MCHBAR_RAPL_PPL) = limit.lo & ~PKG_POWER_LIMIT_EN; + MCHBAR32(MCHBAR_RAPL_PPL + 4) = limit.hi & ~PKG_POWER_LIMIT_EN; } static void soc_init(void *data) |