diff options
| author | Michael Niewöhner <foss@mniewoehner.de> | 2019-11-02 12:20:53 +0100 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-11-20 13:35:08 +0000 |
| commit | 1c6ea92e6fcee21aa01a20500594a09ab14caa74 (patch) | |
| tree | b03c96ef794a6f2ba7383d4261e2826b9d8a350d /src/soc/intel/apollolake/chip.c | |
| parent | 35e76dde7708d0646c56eaf3b5c063b27d2add62 (diff) | |
soc/intel/common: pmclib: make use of the new ETR address API
Make use of the new ETR address API in the ETR3 register related
functions.
Further, disabling and locking of global reset is now done at once to
save one read-modify-write cycle, thus the function was renamed
accordingly and the now redundant disabling in soc/apl got removed.
Change-Id: I49f59efb4a7c7d3d629ac54a7922bbcc8a87714d
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36570
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc/intel/apollolake/chip.c')
| -rw-r--r-- | src/soc/intel/apollolake/chip.c | 4 |
1 files changed, 1 insertions, 3 deletions
diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c index 1aab8a1b7a..6c195bb6fd 100644 --- a/src/soc/intel/apollolake/chip.c +++ b/src/soc/intel/apollolake/chip.c @@ -418,10 +418,8 @@ static void soc_init(void *data) static void soc_final(void *data) { - /* Disable global reset, just in case */ - pmc_global_reset_enable(0); /* Make sure payload/OS can't trigger global reset */ - pmc_global_reset_lock(); + pmc_global_reset_disable_and_lock(); } static void disable_dev(struct device *dev, FSP_S_CONFIG *silconfig) |