diff options
| author | Lance Zhao <lijian.zhao@intel.com> | 2016-04-19 18:04:21 -0700 |
|---|---|---|
| committer | Aaron Durbin <adurbin@chromium.org> | 2016-04-28 05:47:30 +0200 |
| commit | 1bd0c0c4971ce50426cbe18e93e2ec9dca320af1 (patch) | |
| tree | ede27d29edc980ed7cd8ca393f8716b50dc52ee4 /src/soc/intel/apollolake/chip.c | |
| parent | 164e8f1d9b9a36ccca2feefa0e2172ac0c3254c3 (diff) | |
soc/intel/apollolake: Add handling of GNVS ACPI entry for CHROMEOS builds
Add chromeos required GNVS feature. The GNVS table stays in both CBMEM
and ACPI DSDT tables.
Change-Id: I4db0eb18d2de62917a94704318a7896c04e4777f
Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-on: https://review.coreboot.org/14471
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc/intel/apollolake/chip.c')
| -rw-r--r-- | src/soc/intel/apollolake/chip.c | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c index d2a1e0d09f..6e0a90f0fd 100644 --- a/src/soc/intel/apollolake/chip.c +++ b/src/soc/intel/apollolake/chip.c @@ -17,6 +17,7 @@ */ #include <bootstate.h> +#include <cbmem.h> #include <console/console.h> #include <cpu/cpu.h> #include <device/device.h> @@ -26,6 +27,7 @@ #include <memrange.h> #include <soc/iomap.h> #include <soc/cpu.h> +#include <soc/nvs.h> #include <soc/pci_devs.h> #include "chip.h" @@ -65,11 +67,15 @@ static void enable_dev(device_t dev) static void soc_init(void *data) { struct range_entry range; + struct global_nvs_t *gnvs; /* TODO: tigten this resource range */ /* TODO: fix for S3 resume, as this would corrupt OS memory */ range_entry_init(&range, 0x200000, 4ULL*GiB, 0); fsp_silicon_init(&range); + + /* Allocate ACPI NVS in CBMEM */ + gnvs = cbmem_add(CBMEM_ID_ACPI_GNVS, sizeof(*gnvs)); } void platform_fsp_silicon_init_params_cb(struct FSPS_UPD *silupd) |