diff options
| author | Aaron Durbin <adurbin@chromium.org> | 2016-10-25 10:14:32 -0500 |
|---|---|---|
| committer | Aaron Durbin <adurbin@chromium.org> | 2016-10-25 19:27:50 +0200 |
| commit | 06590a20142249ef11e306dc8f4f3469e4847b5a (patch) | |
| tree | d4c3ced4808ee6ce9768c9d01021d98b1c17b61b /src/soc/intel/apollolake/chip.c | |
| parent | 79daac98903360db656c49f0078a2bd1744ca25b (diff) | |
Revert "soc/apollolake: Add soc core init"
This reverts commit a52f883b100f3229dd4d86c81c08781993861f73
(https://review.coreboot.org/16587).
The above commit caused another sever kernel boot regression upwards
of 2 minutes to get through kernel init on quad core systems.
BUG=chrome-os-partner:58994
Change-Id: Id4abc332bf2266e3b3b7be714371ce9cf329bcd9
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/17121
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
Diffstat (limited to 'src/soc/intel/apollolake/chip.c')
| -rw-r--r-- | src/soc/intel/apollolake/chip.c | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c index d722992c58..181d4d68bc 100644 --- a/src/soc/intel/apollolake/chip.c +++ b/src/soc/intel/apollolake/chip.c @@ -461,7 +461,6 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *silupd) silconfig->EmmcRxCmdDataCntl2 = cfg->emmc_rx_cmd_data_cntl2; silconfig->LPSS_S0ixEnable = cfg->lpss_s0ix_enable; - silconfig->SkipMpInit = 1; /* Disable monitor mwait since it is broken due to a hardware bug without a fix */ silconfig->MonitorMwaitEnable = 0; |