summaryrefslogtreecommitdiff
path: root/src/soc/intel/apollolake/car.c
diff options
context:
space:
mode:
authorFurquan Shaikh <furquan@google.com>2019-01-30 22:47:17 -0800
committerFurquan Shaikh <furquan@google.com>2019-02-05 06:31:41 +0000
commitad62b9af651eddf78fd6db37a32f99f429019324 (patch)
treef7e9e8809489e5819a365d03965e388faa60ada2 /src/soc/intel/apollolake/car.c
parentfc63b8bbc0d2f16bc2693c23c50db531382b6ade (diff)
soc/intel/apollolake: Update XHCI ports for GLK in ACPI tables
GLK has a dedicated USB2 port that is used specifically for CNVi BT. This requires that the ACPI tables define an additional USB 2 port which results in _ADR for USB 3 ports being different for GLK than APL. This change splits the ports in xhci.asl into APL and GLK specific ports.asl and selects the appropriate file based on CONFIG_SOC_INTEL_GLK. It also adds support for returning HS09 for GLK if ACPI name is requested for that port. BUG=b:123670712 BRANCH=octopus TEST=Verified that generated DSDT for octopus (GLK) includes HS09 and for reef (APL) does not include HS09 definition. Change-Id: I2d3d3690ec9ea1f6e35c38c3b3cbb82e961b7950 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/31172 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/apollolake/car.c')
0 files changed, 0 insertions, 0 deletions