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authorFurquan Shaikh <furquan@google.com>2016-06-21 12:50:13 -0700
committerFurquan Shaikh <furquan@google.com>2016-06-22 22:20:57 +0200
commit8065bd4ce111c3ff64e0093c7726a76a31dbc29f (patch)
tree83c797e9807718ba4f3aacb84d42bc26687d366d /src/soc/intel/apollolake/bootblock
parent14b2a4d574bbdb069369b81af31d87c5b1016f25 (diff)
intel/apollolake: Add API for get_bios_size and use it
get_bios_size returns the value of bios_size. Use this function to calculate bios_size for caching in bootblock. BUG=chrome-os-partner:54563 Change-Id: I2e592b1c52138bd4623ad2acd05c744224a8e50b Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/15292 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
Diffstat (limited to 'src/soc/intel/apollolake/bootblock')
-rw-r--r--src/soc/intel/apollolake/bootblock/bootblock.c7
1 files changed, 5 insertions, 2 deletions
diff --git a/src/soc/intel/apollolake/bootblock/bootblock.c b/src/soc/intel/apollolake/bootblock/bootblock.c
index deec368129..431dd73bff 100644
--- a/src/soc/intel/apollolake/bootblock/bootblock.c
+++ b/src/soc/intel/apollolake/bootblock/bootblock.c
@@ -22,6 +22,7 @@
#include <soc/iomap.h>
#include <soc/cpu.h>
#include <soc/gpio.h>
+#include <soc/mmap_boot.h>
#include <soc/northbridge.h>
#include <soc/pci_devs.h>
#include <soc/uart.h>
@@ -87,7 +88,8 @@ void asmlinkage bootblock_c_entry(uint64_t base_timestamp)
static void cache_bios_region(void)
{
int mtrr;
- uint32_t rom_size, alignment;
+ size_t rom_size;
+ uint32_t alignment;
mtrr = get_free_var_mtrr();
@@ -95,7 +97,8 @@ static void cache_bios_region(void)
return;
/* Only the IFD BIOS region is memory mapped (at top of 4G) */
- rom_size = CONFIG_IFD_BIOS_END - CONFIG_IFD_BIOS_START;
+ rom_size = get_bios_size();
+
/* Round to power of two */
alignment = 1 << (log2_ceil(rom_size));
rom_size = ALIGN_UP(rom_size, alignment);