soc/apollolake: Add early serial driver for BOOTBLOCK_CONSOLE

Early UART driver is for bootblock and romstage. It is supposed to be used
when BOOTBLOCK_CONSOLE is enabled. This also adds few configuration bits
in bootblock requiered for serial to be set up.

Change-Id: I15520d566f107797e68d618885d4379e73d0fa45
Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-on: https://review.coreboot.org/13677
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

1 files changed, 29 insertions, 1 deletions

diff --git a/src/soc/intel/apollolake/bootblock/bootblock.c b/src/soc/intel/apollolake/bootblock/bootblock.c
index dc0b183bba..d3a78e106f 100644
--- a/src/soc/intel/apollolake/bootblock/bootblock.c
+++ b/src/soc/intel/apollolake/bootblock/bootblock.c
@@ -1,6 +1,34 @@
-#include <soc/bootblock.h>
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2016 Intel Corp.
+ * (Written by Andrey Petrov <andrey.petrov@intel.com> for Intel Corp.)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
 #include <arch/cpu.h>
+#include <bootblock_common.h>
+#include <device/pci.h>
+#include <soc/bootblock.h>
+#include <soc/northbridge.h>
+#include <soc/pci_devs.h>
 
 void asmlinkage bootblock_c_entry(void)
 {
+	device_t dev = NB_DEV_ROOT;
+
+	/* Set PCI Express BAR */
+	pci_io_write_config32(dev, PCIEXBAR, CONFIG_MMCONF_BASE_ADDRESS | 1);
+
+	dev = P2SB_DEV;
+	/* BAR and MMIO enable for IOSF, so that GPIOs can be configured */
+	pci_write_config32(dev, PCI_BASE_ADDRESS_0, CONFIG_IOSF_BASE_ADDRESS);
+	pci_write_config32(dev, PCI_BASE_ADDRESS_1, 0);
+	pci_write_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY);
+
+	/* Call lib/bootblock.c main */
+	main();
 }