diff options
| author | Subrata Banik <subrata.banik@intel.com> | 2017-03-14 18:26:27 +0530 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2017-03-28 18:29:43 +0200 |
| commit | 7952e283fb6dac19a10112199814c80619a28366 (patch) | |
| tree | 0b7ffb6932759a02bf5016e0999290c7eb11d2e4 /src/soc/intel/apollolake/bootblock | |
| parent | 93ebe499d45679a250de780d8a8b73d32d7ea00e (diff) | |
soc/intel/apollolake: Clean up code by using common System Agent module
This patch currently contains the SA initialization
required for bootblock phase -
1. Use SOC_INTEL_COMMON_BLOCK_SA kconfig for common SA code.
2. Perform PCIEXBAR programming based on soc configurable
PCIEX_LENGTH_xxxMB
3. Use common systemagent header file.
Change-Id: I01a24e2d4f1c8c9ca113c128bb6b3eac23dc79ad
Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com>
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/18567
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
Diffstat (limited to 'src/soc/intel/apollolake/bootblock')
| -rw-r--r-- | src/soc/intel/apollolake/bootblock/bootblock.c | 16 |
1 files changed, 5 insertions, 11 deletions
diff --git a/src/soc/intel/apollolake/bootblock/bootblock.c b/src/soc/intel/apollolake/bootblock/bootblock.c index ed4530ce76..dc17b15ad7 100644 --- a/src/soc/intel/apollolake/bootblock/bootblock.c +++ b/src/soc/intel/apollolake/bootblock/bootblock.c @@ -18,6 +18,7 @@ #include <bootblock_common.h> #include <cpu/x86/mtrr.h> #include <device/pci.h> +#include <intelblocks/systemagent.h> #include <lib.h> #include <soc/iomap.h> #include <soc/cpu.h> @@ -25,7 +26,7 @@ #include <soc/gpio.h> #include <soc/iosf.h> #include <soc/mmap_boot.h> -#include <soc/northbridge.h> +#include <soc/systemagent.h> #include <soc/pci_devs.h> #include <soc/pm.h> #include <soc/uart.h> @@ -51,16 +52,9 @@ static void enable_cmos_upper_bank(void) asmlinkage void bootblock_c_entry(uint64_t base_timestamp) { - device_t dev = SA_DEV_ROOT; - - /* Set PCI Express BAR */ - pci_io_write_config32(dev, PCIEXBAR, CONFIG_MMCONF_BASE_ADDRESS | 1); - /* - * Clear TSEG register - TSEG register comes out of reset with a - * non-zero default value. Clear this register to ensure that there are - * no surprises in CBMEM handling. - */ - pci_write_config32(dev, TSEG, 0); + device_t dev; + + bootblock_systemagent_early_init(); dev = PCH_DEV_P2SB; /* BAR and MMIO enable for IOSF, so that GPIOs can be configured */ |