diff options
| author | Andrey Petrov <andrey.petrov@intel.com> | 2016-06-22 18:58:14 -0700 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2016-06-24 20:32:19 +0200 |
| commit | 33fd66b46309b140ed9b228083a55a394117afea (patch) | |
| tree | 6584a3b887dfcc29235c264960b7a9c1d0c97105 /src/soc/intel/apollolake/bootblock | |
| parent | 0f593c22a8a88068ffdf73f87ee9ce98c343a977 (diff) | |
soc/intel/apollolake: Move PMC BAR setup to bootblock
Some features of PMC needs to be accessed before romstage. Hence,
move PMC BARs setup into bootblock.
BUG=chrome-os-partner:54149
BRANCH=none
TEST=none
Change-Id: I14493498314ef1a4ce383e192edccf65fed2d2cb
Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-on: https://review.coreboot.org/15332
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
Diffstat (limited to 'src/soc/intel/apollolake/bootblock')
| -rw-r--r-- | src/soc/intel/apollolake/bootblock/bootblock.c | 17 |
1 files changed, 17 insertions, 0 deletions
diff --git a/src/soc/intel/apollolake/bootblock/bootblock.c b/src/soc/intel/apollolake/bootblock/bootblock.c index 431dd73bff..84130756ed 100644 --- a/src/soc/intel/apollolake/bootblock/bootblock.c +++ b/src/soc/intel/apollolake/bootblock/bootblock.c @@ -134,8 +134,25 @@ static void enable_spibar(void) spi_init(); } +static void enable_pmcbar(void) +{ + device_t pmc = PMC_DEV; + + /* Set PMC base addresses and enable decoding. */ + pci_write_config32(pmc, PCI_BASE_ADDRESS_0, PMC_BAR0); + pci_write_config32(pmc, PCI_BASE_ADDRESS_1, 0); /* 64-bit BAR */ + pci_write_config32(pmc, PCI_BASE_ADDRESS_2, PMC_BAR1); + pci_write_config32(pmc, PCI_BASE_ADDRESS_3, 0); /* 64-bit BAR */ + pci_write_config16(pmc, PCI_BASE_ADDRESS_4, ACPI_PMIO_BASE); + pci_write_config16(pmc, PCI_COMMAND, + PCI_COMMAND_IO | PCI_COMMAND_MEMORY | + PCI_COMMAND_MASTER); +} + void bootblock_soc_early_init(void) { + enable_pmcbar(); + /* Prepare UART for serial console. */ if (IS_ENABLED(CONFIG_SOC_UART_DEBUG)) soc_console_uart_init(); |