intel/apollolake: Fix whitespace issues

Change-Id: Ia5bcd19d994e23375d7e6d2050113c809ae57296
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/14368
Tested-by: build bot (Jenkins)
Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>

5 files changed, 215 insertions, 216 deletions

diff --git a/src/soc/intel/apollolake/acpi/lpss.asl b/src/soc/intel/apollolake/acpi/lpss.asl
index a4cb2cf29e..ab97374ddb 100644
--- a/src/soc/intel/apollolake/acpi/lpss.asl
+++ b/src/soc/intel/apollolake/acpi/lpss.asl
@@ -17,100 +17,100 @@
 
 scope (\_SB.PCI0) {
 
-/* LPIO1 PWM */
-Device(PWM) {
-	Name (_ADR, 0x001A0000)
-	Name (_DDN, "Intel(R) PWM Controller")
-}
-
-/* LPIO1 HS-UART #1 */
-Device(URT1) {
-	Name (_ADR, 0x00180000)
-	Name (_DDN, "Intel(R) HS-UART Controller #1")
-}
-
-/* LPIO1 HS-UART #2 */
-Device(URT2) {
-	Name (_ADR, 0x00180001)
-	Name (_DDN, "Intel(R) HS-UART Controller #2")
-}
-
-/* LPIO1 HS-UART #3 */
-Device(URT3) {
-	Name (_ADR, 0x00180002)
-	Name (_DDN, "Intel(R) HS-UART Controller #3")
-}
-
-/* LPIO1 HS-UART #4 */
-Device(URT4) {
-	Name (_ADR, 0x00180003)
-	Name (_DDN, "Intel(R) HS-UART Controller #4")
-}
-
-/* LPIO1 SPI */
-Device(SPI1) {
-	Name (_ADR, 0x00190000)
-	Name (_DDN, "Intel(R) SPI Controller #1")
-}
-
-/* LPIO1 SPI #2 */
-Device(SPI2) {
-	Name (_ADR, 0x00190001)
-	Name (_DDN, "Intel(R) SPI Controller #2")
-}
-
-/* LPIO1 SPI #3 */
-Device(SPI3) {
-	Name (_ADR, 0x00190002)
-	Name (_DDN, "Intel(R) SPI Controller #3")
-}
-
-
-/* LPIO2 I2C #0 */
-Device(I2C0) {
-	Name (_ADR, 0x00160000)
-	Name (_DDN, "Intel(R) I2C Controller #0")
-}
-
-/* LPIO2 I2C #1 */
-Device(I2C1) {
-	Name (_ADR, 0x00160001)
-	Name (_DDN, "Intel(R) I2C Controller #1")
-}
-
-/* LPIO2 I2C #2 */
-Device(I2C2) {
-	Name (_ADR, 0x00160002)
-	Name (_DDN, "Intel(R) I2C Controller #2")
-}
-
-/* LPIO2 I2C #3 */
-Device(I2C3) {
-	Name (_ADR, 0x00160003)
-	Name (_DDN, "Intel(R) I2C Controller #3")
-}
-
-/* LPIO2 I2C #4 */
-Device(I2C4) {
-	Name (_ADR, 0x00170000)
-	Name (_DDN, "Intel(R) I2C Controller #4")
-}
-
-/* LPIO2 I2C #5 */
-Device(I2C5) {
-	Name (_ADR, 0x00170001)
-	Name (_DDN, "Intel(R) I2C Controller #5")
-}
-
-/* LPIO2 I2C #6 */
-Device(I2C6) {
-	Name (_ADR, 0x00170002)
-	Name (_DDN, "Intel(R) I2C Controller #6")
-}
-
-/* LPIO2 I2C #7 */
-Device(I2C7) {
-	Name (_ADR, 0x00170003)
-	Name (_DDN, "Intel(R) I2C Controller #7")
-}
+	/* LPIO1 PWM */
+	Device(PWM) {
+		Name (_ADR, 0x001A0000)
+		Name (_DDN, "Intel(R) PWM Controller")
+	}
+
+	/* LPIO1 HS-UART #1 */
+	Device(URT1) {
+		Name (_ADR, 0x00180000)
+		Name (_DDN, "Intel(R) HS-UART Controller #1")
+	}
+
+	/* LPIO1 HS-UART #2 */
+	Device(URT2) {
+		Name (_ADR, 0x00180001)
+		Name (_DDN, "Intel(R) HS-UART Controller #2")
+	}
+
+	/* LPIO1 HS-UART #3 */
+	Device(URT3) {
+		Name (_ADR, 0x00180002)
+		Name (_DDN, "Intel(R) HS-UART Controller #3")
+	}
+
+	/* LPIO1 HS-UART #4 */
+	Device(URT4) {
+		Name (_ADR, 0x00180003)
+		Name (_DDN, "Intel(R) HS-UART Controller #4")
+	}
+
+	/* LPIO1 SPI */
+	Device(SPI1) {
+		Name (_ADR, 0x00190000)
+		Name (_DDN, "Intel(R) SPI Controller #1")
+	}
+
+	/* LPIO1 SPI #2 */
+	Device(SPI2) {
+		Name (_ADR, 0x00190001)
+		Name (_DDN, "Intel(R) SPI Controller #2")
+	}
+
+	/* LPIO1 SPI #3 */
+	Device(SPI3) {
+		Name (_ADR, 0x00190002)
+		Name (_DDN, "Intel(R) SPI Controller #3")
+	}
+
+
+	/* LPIO2 I2C #0 */
+	Device(I2C0) {
+		Name (_ADR, 0x00160000)
+		Name (_DDN, "Intel(R) I2C Controller #0")
+	}
+
+	/* LPIO2 I2C #1 */
+	Device(I2C1) {
+		Name (_ADR, 0x00160001)
+		Name (_DDN, "Intel(R) I2C Controller #1")
+	}
+
+	/* LPIO2 I2C #2 */
+	Device(I2C2) {
+		Name (_ADR, 0x00160002)
+		Name (_DDN, "Intel(R) I2C Controller #2")
+	}
+
+	/* LPIO2 I2C #3 */
+	Device(I2C3) {
+		Name (_ADR, 0x00160003)
+		Name (_DDN, "Intel(R) I2C Controller #3")
+	}
+
+	/* LPIO2 I2C #4 */
+	Device(I2C4) {
+		Name (_ADR, 0x00170000)
+		Name (_DDN, "Intel(R) I2C Controller #4")
+	}
+
+	/* LPIO2 I2C #5 */
+	Device(I2C5) {
+		Name (_ADR, 0x00170001)
+		Name (_DDN, "Intel(R) I2C Controller #5")
+	}
+
+	/* LPIO2 I2C #6 */
+	Device(I2C6) {
+		Name (_ADR, 0x00170002)
+		Name (_DDN, "Intel(R) I2C Controller #6")
+	}
+
+	/* LPIO2 I2C #7 */
+	Device(I2C7) {
+		Name (_ADR, 0x00170003)
+		Name (_DDN, "Intel(R) I2C Controller #7")
+	}
 }
diff --git a/src/soc/intel/apollolake/acpi/northbridge.asl b/src/soc/intel/apollolake/acpi/northbridge.asl
index 58ad451ae2..8415ffe8ad 100644
--- a/src/soc/intel/apollolake/acpi/northbridge.asl
+++ b/src/soc/intel/apollolake/acpi/northbridge.asl
@@ -15,10 +15,10 @@
  * GNU General Public License for more details.
  */
 
-        Name(_HID, EISAID("PNP0A08"))	/* PCIe */
-        Name(_CID, EISAID("PNP0A03"))	/* PCI */
-        Name(_ADR, 0)
-        Name(_BBN, 0)
+	Name(_HID, EISAID("PNP0A08"))	/* PCIe */
+	Name(_CID, EISAID("PNP0A03"))	/* PCI */
+	Name(_ADR, 0)
+	Name(_BBN, 0)
 
 Device (MCHC)
 {
@@ -81,51 +81,52 @@ Device (MCHC)
 				NonCacheable, ReadWrite,
 				0x00000000, 0x10000, 0x1ffff, 0x00000000,
 				0x10000,,, PM02)
-})
+	})
 
-/* Current Resource Settings */
-Method (_CRS, 0, Serialized)
-{
+	/* Current Resource Settings */
+	Method (_CRS, 0, Serialized)
+	{
 
-	/* Find PCI resource area in MCRS */
-	CreateDwordField (MCRS, ^PM01._MIN, PMIN)
-	CreateDwordField (MCRS, ^PM01._MAX, PMAX)
-	CreateDwordField (MCRS, ^PM01._LEN, PLEN)
-
-	/* Read C-Unit PCI CFG Reg. 0xBC for TOLUD (shadow from B-Unit) */
-	And(^TLUD, 0xFFF00000, PMIN)
-	/* Read MMCONF base */
-	And(^MCNF, 0xF0000000, PMAX)
-
-	/* Calculate PCI MMIO Length */
-	Add(Subtract(PMAX, PMIN), 1, PLEN)
-
-	/* Find GFX resource area in GCRS */
-	CreateDwordField(MCRS, ^STOM._MIN, GMIN)
-	CreateDwordField(MCRS, ^STOM._MAX, GMAX)
-	CreateDwordField(MCRS, ^STOM._LEN, GLEN)
-
-	/* Read BGSM */
-	And(^BGSM, 0xFFF00000, GMIN)
-
-	/* Read TOLUD */
-	And(^TLUD, 0xFFF00000, GMAX)
-	Decrement(GMAX)
-	Add(Subtract(GMAX, GMIN), 1, GLEN)
-
-	/* Patch PM02 range based on Memory Size */
-	CreateQwordField (MCRS, ^PM02._MIN, MMIN)
-	CreateQwordField (MCRS, ^PM02._MAX, MMAX)
-	CreateQwordField (MCRS, ^PM02._LEN, MLEN)
-
-	Store (^TUUD, Local0)
-	If (LLessEqual (Local0, 0x1000000000))
-        {
-		Store (0, MMIN)
-		Store (0, MLEN)
-	}
-	Subtract (Add (MMIN, MLEN), 1, MMAX)
+		/* Find PCI resource area in MCRS */
+		CreateDwordField (MCRS, ^PM01._MIN, PMIN)
+		CreateDwordField (MCRS, ^PM01._MAX, PMAX)
+		CreateDwordField (MCRS, ^PM01._LEN, PLEN)
 
-	Return (MCRS)
-}
+		/* Read C-Unit PCI CFG Reg. 0xBC for TOLUD (shadow from B-Unit) */
+		And(^TLUD, 0xFFF00000, PMIN)
+		/* Read MMCONF base */
+		And(^MCNF, 0xF0000000, PMAX)
+
+		/* Calculate PCI MMIO Length */
+		Add(Subtract(PMAX, PMIN), 1, PLEN)
+
+		/* Find GFX resource area in GCRS */
+		CreateDwordField(MCRS, ^STOM._MIN, GMIN)
+		CreateDwordField(MCRS, ^STOM._MAX, GMAX)
+		CreateDwordField(MCRS, ^STOM._LEN, GLEN)
+
+		/* Read BGSM */
+		And(^BGSM, 0xFFF00000, GMIN)
+
+		/* Read TOLUD */
+		And(^TLUD, 0xFFF00000, GMAX)
+		Decrement(GMAX)
+		Add(Subtract(GMAX, GMIN), 1, GLEN)
+
+		/* Patch PM02 range based on Memory Size */
+		CreateQwordField (MCRS, ^PM02._MIN, MMIN)
+		CreateQwordField (MCRS, ^PM02._MAX, MMAX)
+		CreateQwordField (MCRS, ^PM02._LEN, MLEN)
+
+		Store (^TUUD, Local0)
+
+		If (LLessEqual (Local0, 0x1000000000))
+		{
+			Store (0, MMIN)
+			Store (0, MLEN)
+		}
+		Subtract (Add (MMIN, MLEN), 1, MMAX)
+
+		Return (MCRS)
+	}
 }
diff --git a/src/soc/intel/apollolake/acpi/pci_irqs.asl b/src/soc/intel/apollolake/acpi/pci_irqs.asl
index 7ebb9fcc7d..22878c673f 100644
--- a/src/soc/intel/apollolake/acpi/pci_irqs.asl
+++ b/src/soc/intel/apollolake/acpi/pci_irqs.asl
@@ -21,44 +21,43 @@ Method(_PRT)
 {
 	Return(Package() {
 
-	       Package(){0x0000FFFF, 0, 0, NPK_INT},
-	       Package(){0x0000FFFF, 1, 0, PUNIT_INT},
-	       Package(){0x0002FFFF, 0, 0, GEN_INT},
-	       Package(){0x0003FFFF, 0, 0, IUNIT_INT},
-	       Package(){0x000DFFFF, 1, 0, PMC_INT},
-	       Package(){0x000EFFFF, 0, 0, AUDIO_INT},
-	       Package(){0x000FFFFF, 0, 0, CSE_INT},
-	       Package(){0x0011FFFF, 0, 0, ISH_INT},
-	       Package(){0x0012FFFF, 0, 0, SATA_INT},
-	       Package(){0x0013FFFF, 0, 0, PIRQA_INT},
-	       Package(){0x0013FFFF, 1, 0, PIRQB_INT},
-	       Package(){0x0013FFFF, 2, 0, PIRQC_INT},
-	       Package(){0x0013FFFF, 3, 0, PIRQD_INT},
-	       Package(){0x0014FFFF, 0, 0, PIRQB_INT},
-	       Package(){0x0014FFFF, 1, 0, PIRQC_INT},
-	       Package(){0x0014FFFF, 2, 0, PIRQD_INT},
-	       Package(){0x0014FFFF, 3, 0, PIRQA_INT},
-	       Package(){0x0015FFFF, 0, 0, XHCI_INT},
-	       Package(){0x0015FFFF, 1, 0, XDCI_INT},
-	       Package(){0x0016FFFF, 0, 0, I2C0_INT},
-	       Package(){0x0016FFFF, 1, 0, I2C1_INT},
-	       Package(){0x0016FFFF, 2, 0, I2C2_INT},
-	       Package(){0x0016FFFF, 3, 0, I2C3_INT},
-	       Package(){0x0017FFFF, 0, 0, I2C4_INT},
-	       Package(){0x0017FFFF, 1, 0, I2C5_INT},
-	       Package(){0x0017FFFF, 2, 0, I2C6_INT},
-	       Package(){0x0017FFFF, 3, 0, I2C7_INT},
-	       Package(){0x0018FFFF, 0, 0, UART0_INT},
-	       Package(){0x0018FFFF, 1, 0, UART1_INT},
-	       Package(){0x0018FFFF, 2, 0, UART2_INT},
-	       Package(){0x0018FFFF, 3, 0, UART3_INT},
-	       Package(){0x0019FFFF, 0, 0, SPI0_INT},
-	       Package(){0x0019FFFF, 1, 0, SPI1_INT},
-	       Package(){0x0019FFFF, 2, 0, SPI2_INT},
-	       Package(){0x001BFFFF, 0, 0, SDCARD_INT},
-	       Package(){0x001CFFFF, 0, 0, EMMC_INT},
-	       Package(){0x001EFFFF, 0, 0, SDIO_INT},
-	       Package(){0x001FFFFF, 1, 0, SMBUS_INT},
-	       }
-	)
+		Package(){0x0000FFFF, 0, 0, NPK_INT},
+		Package(){0x0000FFFF, 1, 0, PUNIT_INT},
+		Package(){0x0002FFFF, 0, 0, GEN_INT},
+		Package(){0x0003FFFF, 0, 0, IUNIT_INT},
+		Package(){0x000DFFFF, 1, 0, PMC_INT},
+		Package(){0x000EFFFF, 0, 0, AUDIO_INT},
+		Package(){0x000FFFFF, 0, 0, CSE_INT},
+		Package(){0x0011FFFF, 0, 0, ISH_INT},
+		Package(){0x0012FFFF, 0, 0, SATA_INT},
+		Package(){0x0013FFFF, 0, 0, PIRQA_INT},
+		Package(){0x0013FFFF, 1, 0, PIRQB_INT},
+		Package(){0x0013FFFF, 2, 0, PIRQC_INT},
+		Package(){0x0013FFFF, 3, 0, PIRQD_INT},
+		Package(){0x0014FFFF, 0, 0, PIRQB_INT},
+		Package(){0x0014FFFF, 1, 0, PIRQC_INT},
+		Package(){0x0014FFFF, 2, 0, PIRQD_INT},
+		Package(){0x0014FFFF, 3, 0, PIRQA_INT},
+		Package(){0x0015FFFF, 0, 0, XHCI_INT},
+		Package(){0x0015FFFF, 1, 0, XDCI_INT},
+		Package(){0x0016FFFF, 0, 0, I2C0_INT},
+		Package(){0x0016FFFF, 1, 0, I2C1_INT},
+		Package(){0x0016FFFF, 2, 0, I2C2_INT},
+		Package(){0x0016FFFF, 3, 0, I2C3_INT},
+		Package(){0x0017FFFF, 0, 0, I2C4_INT},
+		Package(){0x0017FFFF, 1, 0, I2C5_INT},
+		Package(){0x0017FFFF, 2, 0, I2C6_INT},
+		Package(){0x0017FFFF, 3, 0, I2C7_INT},
+		Package(){0x0018FFFF, 0, 0, UART0_INT},
+		Package(){0x0018FFFF, 1, 0, UART1_INT},
+		Package(){0x0018FFFF, 2, 0, UART2_INT},
+		Package(){0x0018FFFF, 3, 0, UART3_INT},
+		Package(){0x0019FFFF, 0, 0, SPI0_INT},
+		Package(){0x0019FFFF, 1, 0, SPI1_INT},
+		Package(){0x0019FFFF, 2, 0, SPI2_INT},
+		Package(){0x001BFFFF, 0, 0, SDCARD_INT},
+		Package(){0x001CFFFF, 0, 0, EMMC_INT},
+		Package(){0x001EFFFF, 0, 0, SDIO_INT},
+		Package(){0x001FFFFF, 1, 0, SMBUS_INT},
+	})
 }
diff --git a/src/soc/intel/apollolake/acpi/soc_int.asl b/src/soc/intel/apollolake/acpi/soc_int.asl
index a97128eb9b..83a831fcd2 100644
--- a/src/soc/intel/apollolake/acpi/soc_int.asl
+++ b/src/soc/intel/apollolake/acpi/soc_int.asl
@@ -15,15 +15,15 @@
  * GNU General Public License for more details.
  */
 
-#ifndef	_SOC_INT_DEFINE_ASL_
-#define	_SOC_INT_DEFINE_ASL_
+#ifndef _SOC_INT_DEFINE_ASL_
+#define _SOC_INT_DEFINE_ASL_
 
-#define	SDCARD_INT	3	/* Need to be shared by PMC and SCC only*/
-#define	UART0_INT	4	/* Need to be shared by PMC and SCC only*/
-#define	UART1_INT	5	/* Need to be shared by PMC and SCC only*/
-#define	UART2_INT	6	/* Need to be shared by PMC and SCC only*/
-#define	UART3_INT	7	/* Need to be shared by PMC and SCC only*/
-#define	XDCI_INT	13	/* Need to be shared by PMC and SCC only*/
+#define SDCARD_INT	3	/* Need to be shared by PMC and SCC only*/
+#define UART0_INT	4	/* Need to be shared by PMC and SCC only*/
+#define UART1_INT	5	/* Need to be shared by PMC and SCC only*/
+#define UART2_INT	6	/* Need to be shared by PMC and SCC only*/
+#define UART3_INT	7	/* Need to be shared by PMC and SCC only*/
+#define XDCI_INT	13	/* Need to be shared by PMC and SCC only*/
 #define NPK_INT		16
 #define PIRQA_INT	16
 #define PIRQB_INT	17
@@ -31,27 +31,26 @@
 #define SATA_INT	19
 #define GEN_INT		19
 #define PIRQD_INT	19
-#define	XHCI_INT	17	/* Need to be shared by PMC and SCC only*/
-#define	SMBUS_INT	20	/* PIRQE */
-#define	CSE_INT		20	/* PIRQE */
-#define	IUNIT_INT	21	/* PIRQF */
-#define	PUNIT_INT	24
-#define	AUDIO_INT	25
-#define	ISH_INT		26
-#define	I2C0_INT	27
-#define	I2C1_INT	28
-#define	I2C2_INT	29
-#define	I2C3_INT	30
-#define	I2C4_INT	31
-#define	I2C5_INT	32
-#define	I2C6_INT	33
-#define	I2C7_INT	34
-#define	SPI0_INT	35
-#define	SPI1_INT	36
-#define	SPI2_INT	37
-#define	UFS_INT		38
-#define	EMMC_INT	39
-#define	SDIO_INT	42
+#define XHCI_INT	17	/* Need to be shared by PMC and SCC only*/
+#define SMBUS_INT	20	/* PIRQE */
+#define CSE_INT		20	/* PIRQE */
+#define IUNIT_INT	21	/* PIRQF */
+#define PUNIT_INT	24
+#define AUDIO_INT	25
+#define ISH_INT		26
+#define I2C0_INT	27
+#define I2C1_INT	28
+#define I2C2_INT	29
+#define I2C3_INT	30
+#define I2C4_INT	31
+#define I2C5_INT	32
+#define I2C6_INT	33
+#define I2C7_INT	34
+#define SPI0_INT	35
+#define SPI1_INT	36
+#define SPI2_INT	37
+#define UFS_INT		38
+#define EMMC_INT	39
+#define SDIO_INT	42
 
-
-#endif	/* _SOC_INT_DEFINE_ASL_ */
\ No newline at end of file
+#endif	/* _SOC_INT_DEFINE_ASL_ */
diff --git a/src/soc/intel/apollolake/acpi/southbridge.asl b/src/soc/intel/apollolake/acpi/southbridge.asl
index 1d9ee9588a..cc526763c6 100644
--- a/src/soc/intel/apollolake/acpi/southbridge.asl
+++ b/src/soc/intel/apollolake/acpi/southbridge.asl
@@ -16,4 +16,4 @@
  */
 
 /* LPSS device */
-#include "lpss.asl"
\ No newline at end of file
+#include "lpss.asl"