diff options
| author | Furquan Shaikh <furquan@google.com> | 2016-06-13 22:23:49 -0700 |
|---|---|---|
| committer | Furquan Shaikh <furquan@google.com> | 2016-06-15 17:56:52 +0200 |
| commit | d01f5a01e6daf0227bdee5eac1528882255285c1 (patch) | |
| tree | 7926e03e89e45531b801e241844cdaf0a2167df2 /src/soc/intel/apollolake/acpi | |
| parent | eb8b7d6ef4794cadbc34cf97ee3bc53faeeac7cf (diff) | |
intel/apollolake: Add CBMEM console to GNVS
CBMEM console stores all the console logs in CBMEM. Address of this
location in CBMEM where console logs are stored needs to be passed up to
OS using GNVS.
1. Add CBMC to GNVS fields in globalnvs.asl
2. Add cbmc member to global_nvs_t structure in nvs.h
3. Initialize gnvs->cbmc to address of cbmem console
BUG=chrome-os-partner:54342
Change-Id: Idcd4573e626fa433c1623bdcbe29921de64539b2
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/15177
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
Diffstat (limited to 'src/soc/intel/apollolake/acpi')
| -rw-r--r-- | src/soc/intel/apollolake/acpi/globalnvs.asl | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/soc/intel/apollolake/acpi/globalnvs.asl b/src/soc/intel/apollolake/acpi/globalnvs.asl index e081dcb60b..1799f315ab 100644 --- a/src/soc/intel/apollolake/acpi/globalnvs.asl +++ b/src/soc/intel/apollolake/acpi/globalnvs.asl @@ -33,6 +33,7 @@ Field (GNVS, ByteAcc, NoLock, Preserve) LIDS, 8, // 0x03 - LID State PWRS, 8, // 0x04 - AC Power State DPTE, 8, // 0x05 - Enable DPTF + CBMC, 32, // 0x06 - 0x09 - Coreboot Memory Console /* ChromeOS stuff (0x100 -> 0xfff, size 0xeff) */ Offset (0x100), |