soc/intel/{apl,cnl,icl,skl,tgl}: Make above 4GB MMIO resource proper

This patch ensures coreboot is not publishing above 4GB mmio resource
if soc common config "enable_above_4GB_mmio" not enable.

Publishing unnecessary 4GB above MMIO resource with wrong base and size
is causing problem while working with discrete GPU.

Unable to boot with dGPU on IA platform with below error:

[    2.297425] pcieport 0000:00:1c.0: PCI bridge to [bus 05]
[    2.302858] pcieport 0000:00:1c.0:   bridge window [io  0x2000-0x2fff]
[    2.309427] pcieport 0000:00:1c.0:   bridge window [mem 0xb2000000-0xb20fffff]
[    2.316679] pcieport 0000:00:1c.0:   bridge window [mem 0x840000000-0x8c01fffff 64bit pref]
[    2.325072] pcieport 0000:00:1c.0: PCI bridge to [bus 05]
[    2.330502] pcieport 0000:00:1c.0:   bridge window [io  0x2000-0x2fff]
[    2.337062] pcieport 0000:00:1c.0:   bridge window [mem 0xb2000000-0xb20fffff]
[    2.344317] pcieport 0000:00:1c.0:   bridge window [mem 0xa0000000-0xb01fffff 64bit pref]
[    2.352541] [drm] Not enough PCI address space for a large BAR.

Change-Id: I77b3a0e44582b047d7fbe679d3000d616f7e6111
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38125
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com>

2 files changed, 16 insertions, 14 deletions

diff --git a/src/soc/intel/apollolake/acpi/globalnvs.asl b/src/soc/intel/apollolake/acpi/globalnvs.asl
index 4aad29c81a..1db373d484 100644
--- a/src/soc/intel/apollolake/acpi/globalnvs.asl
+++ b/src/soc/intel/apollolake/acpi/globalnvs.asl
@@ -1,7 +1,7 @@
 /*
  * This file is part of the coreboot project.
  *
- * Copyright (C) 2016 Intel Corp.
+ * Copyright (C) 2016-2020 Intel Corp.
  * (Written by Alexandru Gagniuc <alexandrux.gagniuc@intel.com> for Intel Corp.)
  *
  * This program is free software; you can redistribute it and/or modify
@@ -45,6 +45,9 @@ Field (GNVS, ByteAcc, NoLock, Preserve)
 	EPCS,   8,      // 0x2C - SGX Enabled status
 	EMNA,   64,     // 0x2D - 0x34 EPC base address
 	ELNG,   64,     // 0x35 - 0x3C EPC Length
+	E4GM,	8,	// 0x3D - Enable above 4GB MMIO Resource
+	A4GB,	64,	// 0x3E - 0x45 Base of above 4GB MMIO Resource
+	A4GS,	64,	// 0x46 - 0x4D Length of above 4GB MMIO Resource
 
 	/* ChromeOS stuff (0x100 -> 0xfff, size 0xeff) */
 	Offset (0x100),
diff --git a/src/soc/intel/apollolake/acpi/northbridge.asl b/src/soc/intel/apollolake/acpi/northbridge.asl
index 027e2a623c..ff146ec9db 100644
--- a/src/soc/intel/apollolake/acpi/northbridge.asl
+++ b/src/soc/intel/apollolake/acpi/northbridge.asl
@@ -1,7 +1,7 @@
 /*
  * This file is part of the coreboot project.
  *
- * Copyright (C) 2016 Intel Corp.
+ * Copyright (C) 2016-2020 Intel Corp.
  * (Written by Lance Zhao <lijian.zhao@intel.com> for Intel Corp.)
  *
  * This program is free software; you can redistribute it and/or modify
@@ -15,7 +15,6 @@
  * GNU General Public License for more details.
  */
 
-#define BASE_64GB	0x1000000000
 
 Name(_HID, EISAID("PNP0A08"))	/* PCIe */
 Name(_CID, EISAID("PNP0A03"))	/* PCI */
@@ -115,18 +114,18 @@ Method (_CRS, 0, Serialized)
 	Add(Subtract(GMAX, GMIN), 1, GLEN)
 
 	/* Patch PM02 range based on Memory Size */
-	CreateQwordField (MCRS, PM02._MIN, MMIN)
-	CreateQwordField (MCRS, PM02._MAX, MMAX)
-	CreateQwordField (MCRS, PM02._LEN, MLEN)
-
-	Store (\_SB.PCI0.MCHC.TUUD, Local0)
-
-	If (LLessEqual (Local0, BASE_64GB))
-	{
-		Store (0, MMIN)
-		Store (0, MLEN)
+	If (LEqual (A4GS, 0)) {
+		CreateQwordField (MCRS, PM02._LEN, MSEN)
+		Store (0, MSEN)
+	} Else {
+		CreateQwordField (MCRS, PM02._MIN, MMIN)
+		CreateQwordField (MCRS, PM02._MAX, MMAX)
+		CreateQwordField (MCRS, PM02._LEN, MLEN)
+		/* Set 64bit MMIO resource base and length */
+		Store (A4GS, MLEN)
+		Store (A4GB, MMIN)
+		Subtract (Add (MMIN, MLEN), 1, MMAX)
 	}
-	Subtract (Add (MMIN, MLEN), 1, MMAX)
 
 	Return (MCRS)
 }