diff options
| author | Furquan Shaikh <furquan@chromium.org> | 2017-08-05 11:12:44 -0700 |
|---|---|---|
| committer | Furquan Shaikh <furquan@google.com> | 2017-08-10 16:25:14 +0000 |
| commit | ea4ece61b6fc787c652a193ecd04c075daca3158 (patch) | |
| tree | 44ce6dc1af1cd2f7ef61bd4510e3da694fd9119d /src/soc/intel/apollolake/acpi | |
| parent | 96024836077d28100035950e517b2ae5ad1ab5d9 (diff) | |
soc/intel/apollolake: Enable UART debug controller on S3 resume
1. Add a new variable to GNVS to store information during S3 suspend
whether UART debug controller is enabled.
2. On resume, read stored GNVS variable to decide if UART debug port
controller needs to be initialized.
3. Provide helper functions required by intel/common UARRT driver for
enabling controller on S3 resume.
BUG=b:64030366
Change-Id: Idd17dd0bd3c644383f273b465a16add184e3b171
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/20888
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/apollolake/acpi')
| -rw-r--r-- | src/soc/intel/apollolake/acpi/globalnvs.asl | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/soc/intel/apollolake/acpi/globalnvs.asl b/src/soc/intel/apollolake/acpi/globalnvs.asl index 1548c305eb..6431faee4a 100644 --- a/src/soc/intel/apollolake/acpi/globalnvs.asl +++ b/src/soc/intel/apollolake/acpi/globalnvs.asl @@ -41,6 +41,8 @@ Field (GNVS, ByteAcc, NoLock, Preserve) PRT0, 32, // 0x25 - 0x28 - PERST_0 Address SCDP, 8, // 0x29 - SD_CD GPIO portid SCDO, 8, // 0x2A - GPIO pad offset relative to the community + UIOR, 8, // 0x2B - UART debug controller init on S3 resume + /* ChromeOS stuff (0x100 -> 0xfff, size 0xeff) */ Offset (0x100), #include <vendorcode/google/chromeos/acpi/gnvs.asl> |