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authorSubrata Banik <subrata.banik@intel.com>2017-03-08 17:55:26 +0530
committerMartin Roth <martinroth@google.com>2017-04-10 20:05:35 +0200
commitccd8700cac9bda4229ba5628e6f51ab0b96fde41 (patch)
treebc5b8b94337d609de66b31e603b67e1bed0ca0dd /src/soc/intel/apollolake/acpi/scs.asl
parente7ceae79502705a8dc86943e6296fd2cf7735677 (diff)
soc/intel/apollolake: Use common PCR module
This patch use common PCR library to perform CRRd and CRWr operation using Port Ids, define inside soc/pcr_ids.h Change-Id: Iacbf58dbd55bf3915676d875fcb484362d357a44 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/18673 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc/intel/apollolake/acpi/scs.asl')
-rw-r--r--src/soc/intel/apollolake/acpi/scs.asl4
1 files changed, 2 insertions, 2 deletions
diff --git a/src/soc/intel/apollolake/acpi/scs.asl b/src/soc/intel/apollolake/acpi/scs.asl
index f69f43cda5..bb8b684ef3 100644
--- a/src/soc/intel/apollolake/acpi/scs.asl
+++ b/src/soc/intel/apollolake/acpi/scs.asl
@@ -17,8 +17,8 @@ Scope (\_SB.PCI0) {
/* 0xD6- is the port address */
/* 0x600- is the dynamic clock gating control register offset (GENR) */
OperationRegion (SBMM, SystemMemory,
- Or ( Or (CONFIG_IOSF_BASE_ADDRESS,
- ShiftLeft(0xD6, 16)), 0x0600), 0x18)
+ Or ( Or (CONFIG_PCR_BASE_ADDRESS,
+ ShiftLeft(0xD6, PCR_PORTID_SHIFT)), 0x0600), 0x18)
Field (SBMM, DWordAcc, NoLock, Preserve)
{
GENR, 32,