diff options
author | Shaunak Saha <shaunak.saha@intel.com> | 2016-05-25 11:34:43 -0700 |
---|---|---|
committer | Martin Roth <martinroth@google.com> | 2016-06-01 22:26:21 +0200 |
commit | d6463dd42c0b5688601ce6de5e7cff16926df297 (patch) | |
tree | 82e5f91bac541bffed52255f38c9d9ca0fca5857 /src/soc/intel/apollolake/acpi/lpc.asl | |
parent | 7043bf353af14b5a11f18875e6e41ceac56ebfa7 (diff) |
intel/apollolake: Add support to enable google ChromeEC
ChromeEC is needed for EC controlled features to work properly.
This patch adds neccessary support in soc/intel so that mainboard
asl files can include the ChromeEC e.g. PNOT method and
LPCB and also the nvs fields.
BUG = 53096
TEST = This patch is needed by the mainboard specific ASL change to include
src/ec/google/chromeec/acpi/ec.asl
Change-Id: Icecc437df05cd3efb41579317a353fd22526e0c9
Signed-off-by: Shaunak Saha <shaunak.saha@intel.com>
Reviewed-on: https://review.coreboot.org/14967
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc/intel/apollolake/acpi/lpc.asl')
-rw-r--r-- | src/soc/intel/apollolake/acpi/lpc.asl | 23 |
1 files changed, 23 insertions, 0 deletions
diff --git a/src/soc/intel/apollolake/acpi/lpc.asl b/src/soc/intel/apollolake/acpi/lpc.asl new file mode 100644 index 0000000000..749daf78b1 --- /dev/null +++ b/src/soc/intel/apollolake/acpi/lpc.asl @@ -0,0 +1,23 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* Intel LPC Bus Device - 0:1f.0 */ + +Device (LPCB) +{ + Name (_ADR, 0x001f0000) +} |