diff options
| author | Subrata Banik <subrata.banik@intel.com> | 2020-01-03 15:29:02 +0530 |
|---|---|---|
| committer | Subrata Banik <subrata.banik@intel.com> | 2020-01-10 08:40:57 +0000 |
| commit | b6df6b065cffea9b93f6fdbd041ee15e4ec6fd61 (patch) | |
| tree | 48969f4662f0f458deb8cb47abd321559ff64ee9 /src/soc/intel/apollolake/acpi.c | |
| parent | 1c3086a6036f9908c8c09c823c5ad1718eac7ce0 (diff) | |
soc/intel/{apl,cnl,icl,skl,tgl}: Make above 4GB MMIO resource proper
This patch ensures coreboot is not publishing above 4GB mmio resource
if soc common config "enable_above_4GB_mmio" not enable.
Publishing unnecessary 4GB above MMIO resource with wrong base and size
is causing problem while working with discrete GPU.
Unable to boot with dGPU on IA platform with below error:
[ 2.297425] pcieport 0000:00:1c.0: PCI bridge to [bus 05]
[ 2.302858] pcieport 0000:00:1c.0: bridge window [io 0x2000-0x2fff]
[ 2.309427] pcieport 0000:00:1c.0: bridge window [mem 0xb2000000-0xb20fffff]
[ 2.316679] pcieport 0000:00:1c.0: bridge window [mem 0x840000000-0x8c01fffff 64bit pref]
[ 2.325072] pcieport 0000:00:1c.0: PCI bridge to [bus 05]
[ 2.330502] pcieport 0000:00:1c.0: bridge window [io 0x2000-0x2fff]
[ 2.337062] pcieport 0000:00:1c.0: bridge window [mem 0xb2000000-0xb20fffff]
[ 2.344317] pcieport 0000:00:1c.0: bridge window [mem 0xa0000000-0xb01fffff 64bit pref]
[ 2.352541] [drm] Not enough PCI address space for a large BAR.
Change-Id: I77b3a0e44582b047d7fbe679d3000d616f7e6111
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38125
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com>
Diffstat (limited to 'src/soc/intel/apollolake/acpi.c')
| -rw-r--r-- | src/soc/intel/apollolake/acpi.c | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/src/soc/intel/apollolake/acpi.c b/src/soc/intel/apollolake/acpi.c index 7163884365..46c7b6ce0a 100644 --- a/src/soc/intel/apollolake/acpi.c +++ b/src/soc/intel/apollolake/acpi.c @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2016 Intel Corp. + * Copyright (C) 2016-2020 Intel Corp. * Copyright (C) 2017-2019 Siemens AG * (Written by Lance Zhao <lijian.zhao@intel.com> for Intel Corp.) * @@ -127,6 +127,9 @@ void acpi_create_gnvs(struct global_nvs_t *gnvs) if (CONFIG(SOC_INTEL_COMMON_BLOCK_SGX)) sgx_fill_gnvs(gnvs); + + /* Fill in Above 4GB MMIO resource */ + sa_fill_gnvs(gnvs); } uint32_t acpi_fill_soc_wake(uint32_t generic_pm1_en, |