diff options
| author | Mario Scheithauer <mario.scheithauer@siemens.com> | 2017-09-18 17:08:48 +0200 |
|---|---|---|
| committer | Aaron Durbin <adurbin@chromium.org> | 2017-09-21 14:47:42 +0000 |
| commit | 841416f6f8318f65982c29d376fce2e810045b8d (patch) | |
| tree | b4adec1b0370ec4acdb9771984b30fd9c9dac0e8 /src/soc/intel/apollolake/acpi.c | |
| parent | 09703f64940a66345f27d28c0e339c7ac1864b54 (diff) | |
soc/intel/apollolake: Make SCI configurable
The System Control Interrupt is routed per default to IRQ 9. Some
mainboards use IRQ 9 for different purpose. Therefore it is necessary to
make the SCI configurable on Apollo Lake.
Change-Id: Ib4a7ce7d68a6f1f16f27d0902d83dc8774e785b1
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/21584
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc/intel/apollolake/acpi.c')
| -rw-r--r-- | src/soc/intel/apollolake/acpi.c | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/src/soc/intel/apollolake/acpi.c b/src/soc/intel/apollolake/acpi.c index e4846e4d05..df4e630c7c 100644 --- a/src/soc/intel/apollolake/acpi.c +++ b/src/soc/intel/apollolake/acpi.c @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2016 Intel Corp. + * Copyright 2017 Siemens AG. * (Written by Lance Zhao <lijian.zhao@intel.com> for Intel Corp.) * * This program is free software; you can redistribute it and/or modify @@ -69,6 +70,12 @@ uint32_t soc_read_sci_irq_select(void) return read32((void *)pmc_bar + IRQ_REG); } +void soc_write_sci_irq_select(uint32_t scis) +{ + uintptr_t pmc_bar = soc_read_pmc_base(); + write32((void *)pmc_bar + IRQ_REG, scis); +} + acpi_cstate_t *soc_get_cstate_map(size_t *entries) { *entries = ARRAY_SIZE(cstate_map); |